L4M Device
Level 4 Mapper
TXC-03456
DATA SHEET
FEATURES
• Maps an asynchronous 139.264 Mbit/s tributary
into an AU-4/VC-4 STS-3c/SPE.
• Nibble or byte 139.264 Mbit/s line interface
- G.751 receive and transmit performance
monitoring (frame alignment, distant alarm
indication)
• SDH/SONET bus access
- Drop/add byte buses
- Optional drop bus AU-4 pointer tracking with
framing delay compensation
• SDH/SONET timing mode
- Drop bus timing
- Add bus timing
- External timing with framing delay
compensation
• Microprocessor access
- Intel I/O with separate address/data buses
- Motorola I/O with separate address/data
buses
- Motorola I/O with multiplexed bus
- Interrupt capability with individual mask bits
• POH byte processing
• Enhanced desynchronizer access
• Testing features
- Line loopback
- SDH/SONET loopback
- 2
23
-1 test generator and analyzer
• Boundary scan capability (IEEE 1149.1)
• 144-pin plastic quad flat package
DESCRIPTION
The L4M device maps a 139.264 Mbit/s asynchronous
line signal into an AU-4 VC-4/STS-3c SPE signal. The
SDH/SONET signal is transmitted via the add bus with
timing derived from the drop bus, add bus, or external
clock source. The L4M can compensate for up to a
frame offset when using external timing and an external
C1 pulse. An option is provided to generate TOH bytes,
such as the A1 and A2 framing bytes, a C1 byte, and the
H1 and H2 pointer bytes only in drop bus and external
timing modes. The VC-4/SPE can be fixed to a known J1
reference when add bus timing is selected, or it can be
positioned with a pointer value of 0 or 522 when drop
bus or external timing is selected.
In the drop direction, an optional pointer tracking
machine is provided. In this mode, the L4M can compen-
sate for up to a frame in offset. External access is pro-
vided for the POH bytes, in addition to internal
processing capability. Serial access is provided for the
overhead communications bits in the format. An alarm
indication port is provided for ring configuration applica-
tions.
APPLICATIONS
• Add/drop multiplexers
• Digital cross-connect systems
• Broadband switching systems
• Transmission equipment
SDH/SONET SIDE
Alarm
“O”-Bits Indication
Interface
Control
Port
µP
I/O
LINE SIDE
Transmit Nibble
or Byte Data
Add Bus
L4M
Level 4 Mapper
TXC-03456
Transmit Clock In
Receive Nibble
or Byte Data
Receive Clock Out
Receive Clock In
Drop Bus
VCXO Boundary
POH
Interface Control
Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,265,096; 5,548,534
U.S. and/or foreign patents issued or pending
Copyright
2000 TranSwitch Corporation
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03456-MB
Ed. 1A, January 2000
TranSwitch Corporation
•
3 Enterprise Drive
•
Shelton, Connecticut 06484
Tel: 203-929-8810
•
Fax: 203-926-9453
•
www.transwitch.com
•
USA
DATA SHEET
TABLE OF CONTENTS
Section
Page
Block Diagram ...................................................................................................................................... 3
Block Diagram Description ................................................................................................................... 4
Pin Diagram .......................................................................................................................................... 7
Pin Descriptions .................................................................................................................................... 8
Absolute Maximum Ratings ................................................................................................................ 19
Thermal Characteristics ...................................................................................................................... 19
Power Requirements .......................................................................................................................... 19
Input, Output and I/O Parameters ....................................................................................................... 20
Timing Characteristics ........................................................................................................................ 22
Operation ....................................................................................................................................... 40-61
Internal Device Operation .............................................................................................................. 40
External Device Operation ............................................................................................................. 57
Memory Map ....................................................................................................................................... 62
Memory Map Descriptions .................................................................................................................. 66
Package Information ........................................................................................................................... 89
Ordering Information ........................................................................................................................... 90
Related Products ................................................................................................................................ 90
Standards Documentation Sources .................................................................................................... 91
List of Data Sheet Changes ............................................................................................................... 93
Documentation Update Registration Form* ................................................................................... 95
L4M
TXC-03456
* Please note that TranSwitch provides documentation for all of its products. Customers who are using a
TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to
receive relevant updated and supplemental documentation as it is issued. They should also contact the
Applications Engineering Department to ensure that they are provided with the latest available information
about the product, especially before undertaking development of new designs incorporating the product.
LIST OF FIGURES
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Page
L4M TXC-03456 Block Diagram ....................................................................................... 3
L4M TXC-03456 Pin Diagram .......................................................................................... 7
Transmit Line Interface Timing ....................................................................................... 22
Receive Line Interface Timing ........................................................................................ 23
Add Bus Interface Timing (Add Bus) .............................................................................. 24
Add Bus Interface Timing (External Clock) ..................................................................... 25
Add Bus Interface Timing (Drop Bus Clock and C1) ...................................................... 26
Drop Bus Interface Timing .............................................................................................. 27
Transmit Overhead Comm Channel Timing ................................................................... 28
Receive Overhead Comm Channel Timing .................................................................... 28
Transmit Path Overhead Interface Timing ...................................................................... 29
Receive Path Overhead Interface Timing ....................................................................... 30
Transmit Alarm Indication Port Timing ........................................................................... 31
Receive Alarm Indication Port Timing ............................................................................ 32
Microprocessor Timing Read Cycle - Intel ...................................................................... 33
Microprocessor Timing Write Cycle - Intel ...................................................................... 34
Microprocessor Timing Read Cycle - Motorola .............................................................. 35
Microprocessor Timing Write Cycle - Motorola ............................................................... 36
Microprocessor Timing Read Cycle Multiplex Bus - Motorola ........................................ 37
Microprocessor Timing Write Cycle Multiplex Bus - Motorola ........................................ 38
Boundary Scan Timing .................................................................................................... 39
Pointer Interpretation State Diagram .............................................................................. 41
Test Generator, Analyzer and Loopback......................................................................... 49
Boundary Scan Schematic .............................................................................................. 52
Phase-Locked Loop......................................................................................................... 57
L4M 140 Mbit/s Line Interface ........................................................................................ 58
Use of Two L4M Devices in Ring Configuration .............................................................. 60
L4M TXC-03456 144-Pin Plastic Quad Flat Package .................................................... 89
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TXC-03456-MB
Ed. 1A, January 2000
DATA SHEET
BLOCK DIAGRAM
SDH/SONET SIDE
EXLOS
DROPT
EXC1
EXTC
ENABT
ACLK
AC1J1
AC1
ASPE
ADD
ADn
APAR
RPOHF
RPOHD
RPOHC
TPOHF
TPOHD
TPOHC
TOCHC
TOCHD
ROCHC
ROCHD
BUILD
BLOCK
STUFF/
SYNC
BLOCK
8
INPUT
BLOCK
TXDn
TXC
NIB
ADD
BLOCK
PERFORMANCE
MONITORING
TRANSMIT
FRAME
ALIGNMENT
DETECTOR
TRANSMIT
AIS
DETECTOR
L4M
TXC-03456
LINE SIDE
8
MOTOROLA
MOTOROLA
INTEL (TWO BUSES) (MULTIPLEXED)
POH
I/O
8
8
D7 - D0
Unused
A7 - A0
SEL
RD
WR
RDY
INT
MOTO
MADBUS
RAMCI
D7 - D0
Unused
A7 - A0
SEL
RD/WR
Unused
DTACK
IRQ
MAD7 - MAD0
AS
Unused
SEL
RD/WR
DS
DTACK
IRQ
OVERHEAD
COMM
CHANNEL
I/O
RAM
µP
I/O
RAIPD
TAIPD
TAIPC
TAIPF
RESET
Alarms
PTEN
DCLK
DC1J1
DC1
DSPE
DDn
DPAR
HIGHZ
POHDIS
AISIND
ALARM
INDICATION
PORT
RECEIVE
AIS
DETECTOR
RECEIVE
FRAME
ALIGNMENT
DETECTOR
5
PERFORMANCE
MONITORING
POINTER
TRACKING
BLOCK
8
DECODE
BLOCK
DESTUFF
BLOCK
DESYNC
BLOCK
OUTPUT
BLOCK
RXDn
RXCO
RXCI
DROP
BLOCK
8
Note: n = 7 - 0
BOUNDARY
SCAN
TCK
TMS
TDI
TRS
TDO
DESYNC
SIGNALS
6
Figure 1. L4M TXC-03456 Block Diagram
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TXC-03456-MB
Ed. 1A, January 2000
DATA SHEET
BLOCK DIAGRAM DESCRIPTION
L4M
TXC-03456
A simplified block diagram of the L4M device is shown in Figure 1. A byte-wide or nibble-wide 139.264 Mbit/s
signal (TXDn) is connected to the Input Block. The nibble interface is selected by placing a high on the lead
designated as NIB. Data is clocked into the L4M on positive transitions of the clock signal TXC. A control bit is
provided which enables data to be clocked into the L4M on negative transitions of the clock. The L4M Input
Block also terminates an external loss of signal (EXLOS) indication. A low placed on this lead indicates that an
external line interface device, such as a CMI interface device, has detected a loss of signal. This signal is
reported as an alarm within the L4M for the microprocessor, and can generate an interrupt and a 140 Mbit/s
AIS when enabled.
The 140 Mbit/s transmit line signal is monitored by the two Transmit Performance Monitoring Blocks for ITU-T
G.751 frame alignment and a Distant Alarm Status. A Distant Alarm is defined as a 1 in bit 13 of the G.751
frame format. This alarm can generate an interrupt indication when enabled. When frame alignment is estab-
lished, framing errors are counted in a 16-bit performance counter. The 140 Mbit/s line signal is also monitored
for an Alarm Indication Signal (AIS). The AIS detection circuit can be enabled to work in conjunction with the
frame alignment circuit. An AIS condition is reported as an alarm, and can generate an interrupt when enabled.
The Stuff/Sync Block contains a FIFO and is controlled by write timing from the Input Block, and by read timing
from the Build Block. The FIFO accommodates input and timing jitter as specified in ITU-T Recommendation
G.823. The FIFO is protected against overflow and underflow conditions by reporting a FIFO error alarm, and
will automatically recenter when a FIFO underflow or overflow alarm has been detected. The reset is held for
approximately one frame before the FIFO is released for operation. Upon power-up, or on applying a reset, the
transmit FIFO is also recentered. The stuffing algorithm uses one set of five control bits (C-bits) with one stuff
opportunity bit (S-bit) per subframe (nine subframes) for frequency justification.
The Build Block, with timing signals exchanged with the Stuff/Sync Block, constructs the VC-4 format as illus-
trated below.
1
1
J1
139.264 Mbit/s Build Format
Subframe 1
Subframe 2
P
O
H
9
Subframe 9
R:
C:
S:
O:
I:
Fixed Stuff Bits
Justification Control Bits
Justification Opportunity Bits
Overhead Bits
Information Bits
261
POH W 96I X 96I Y 96I Y 96I Y 96I
W = I I I I I I I I
X = CRRRRROO
Y = RRRRRRRR
Y 96I Y 96I Y 96I X 96I Y 96I
Z = I I I I I I SR
X 96I Y 96I Y 96I Y 96I X 96I
Y 96I Y 96I X 96I Y 96I Z 96I
The L4M can build the 261 column by 9 row VC-4 format without or with path overhead bytes, and "O"-bits,
depending on the features selected. The addition of POH bytes to the VC-4 format is disabled by applying a
low to the pin designated POHDIS (also applying a low to POHDIS disables receive VC-4 POH processing).
The starting position of the VC-4 J1 bytes can be synchronized to the add bus J1 pulse, when add bus timing
is selected, or have a starting location of 0 or 522, when drop bus or the external timing modes are selected.
The L4M can also generate an unequipped or supervisory unequipped VC-4. An unequipped VC-4 is defined
as all zeros for the POH and payload bytes, while a supervisory unequipped VC-4 is defined as having valid
POH bytes, but the payload bytes equal to zero. The Build Block is also responsible for multiplexing individual
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TXC-03456-MB
Ed. 1A, January 2000
DATA SHEET
L4M
TXC-03456
POH bytes from the Path Overhead interface, or from RAM locations written to by the microprocessor, into the
add bus data stream. The RDI state and FEBE count may be provided from a mate L4M for path-protected ring
configurations.
The Add Block uses drop bus timing signals, add bus timing signals, or external timing signals for outputting
the SDH/STS-3c data signal and parity to the add bus. A feature is also provided that generates the A1, A2, C1
and H1/H2 Transport (SDH Section) Overhead bytes, depending upon the timing mode selected. The C1 byte
value may be a fixed or a microprocessor-written value. The SS-bits in the transmitted pointer may be fixed or
written by the microprocessor. Unused Transport Overhead bytes can be selected to be three-stated or forced
to zero. In the add bus timing mode, the clock and C1J1 signals are monitored for operation. In the external
timing mode, an option is provided which can compensate up to a frame for the position of the C1 byte framing
pulse (EXC1).
The Add Block interface for the add bus timing mode consists of an input clock (ACLK), input C1 and J1 indica-
tor (AC1J1), a separate C1 input (AC1) when enabled, an input SPE indicator (ASPE), output byte data (AD7-
AD0), output parity indication (APAR), and an output add data to bus indicator (ADD). When the L4M is config-
ured to operate in the external timing mode, the add bus signals consist of: external reference input clock
(EXTC) and framing signal (EXC1) (optional), an output clock (ACLK), output C1 and J1 indicator (AC1J1), an
output SPE indicator (ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add
data to bus indicator (ADD). When the L4M is configured to operate in the drop bus timing mode, the add bus
signals consist of: an output clock (ACLK), output C1 and J1 indicator (AC1J1), an output SPE indicator
(ASPE), output byte data (AD7-AD0), output parity indication (APAR), and an output add data to bus indicator
(ADD). Odd parity may be calculated over all add bus signals (except the add indicator), or data only.
The Drop Block terminates the drop bus signals. The drop bus signals consists of an input clock (DCLK), input
C1 and J1 indicator (DC1J1), an input SPE indicator (DSPE), input byte data (DD7-DD0), input parity indica-
tion (DPAR), and an optional framing pulse (DC1). When the pointer tracking machine feature is enabled, the
J1 signal in the C1J1 signal must not be present. Odd parity may be checked over all of the drop bus signals,
or for the data byte only. When the pointer tracking machine is enabled, the relative position of C1 can be com-
pensated up to one frame.
The Pointer Tracking Block is enabled by placing a high on the lead designated as PTEN. The pointer tracking
machine meets the pointer tracking requirements specified in ETSI 1015. The Pointer Tracking Block deter-
mines the starting location of the J1 byte in the VC-4 format. The S-bit transition check in the H1 pointer byte
may be disabled in the Pointer Tracking Block. When enabled, the S-bit check can be a fixed value or a value
written by the microprocessor. In addition, the AIS to LOP transition can be disabled to have the Pointer Track-
ing state machine conform to Bellcore standards. The Pointer Tracking Block monitors the pointer bytes for a
path AIS and LOP alarm. Positive, negative and NDF occurrences are counted in 8-bit performance counters.
Having established the starting location of the VC-4, the Decode Block performs Path Overhead byte process-
ing. The POH bytes are written into RAM locations for a microprocessor read cycle in addition to being pro-
vided at a POH interface for external access. Capability is also provided in the L4M for performing the path
trace message comparison for the J1 byte. B3 BIP-8 parity errors and the input FEBE count in the G1 byte are
counted as bit or block errors. The status of the RDI bit is also checked, and an alarm indication provided. The
FEBE count is also provided, along with an RDI indication (as a result of local alarms) to an Alarm Indication
Port for path-protected ring operation. A bit stuffing AIS feature is also provided in addition to using an external
AIS clock to generate line AIS as a result of receive alarms.
The Desynchronizer Block is based on a proprietary TranSwitch design. The Desynchronizer Block removes
the effect on the output signal of systemic jitter due to signal mapping and pointer movements, and consists of
two FIFOs. The FIFOs are monitored for overflow and underflow alarms, and reset automatically when an
alarm is detected. A 15-bit pointer leak register is provided for a microprocessor-written value. The following six
desynchronizer signals are provided: Positive and negative phase detector outputs (CTRL and CTRL), a stuff
indicator (STUFF) that provides the status of the stuff (justification) on a per-subframe basis, positive and neg-
ative justification indicator bits (PJ and NJ), and a pointer leak counter equal to zero indication (PLEQ0). In
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TXC-03456-MB
Ed. 1A, January 2000
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