5P49V5901A708NLGI datasheet, PDF

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5P49V5901A708NLGI: DescriptionClock Generator; CategoryThe embedded processor and controller Microcontrollers and processors; File Size430KB，36 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5P49V5901A708NLGI Overview

Clock Generator

5P49V5901A708NLGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	,
Reach Compliance Code	compliant
ECCN code	EAR99
Peak Reflow Temperature (Celsius)	260
Maximum time at peak reflow temperature	30
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

5P49V5901A708NLGI Preview

Programmable Clock Generator

IDT5P49V5901A

DATASHEET

Description

The IDT5P49V5901A is a programmable clock generator

intended for high performance consumer, networking,

industrial, computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock

5).

The frequencies are generated from a single reference clock.

The reference clock can come from one of the two redundant

clock inputs. A glitchless manual switchover function allows

one of the redundant clocks to be selected during normal

operation.

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

The device may be configured to use one of two I

addresses to allow multiple devices to be used in a system.

Features

•

Generates up to four independent output frequencies

•

High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

•

Four fractional output dividers (FODs)

•

Independent Spread Spectrum capability on each output

pair

•

Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

•

C serial programming interface

•

One reference LVCMOS output clock

•

Four universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os - LVPECL, LVDS and HCSL

•

Pin Assignment

OUT0_SEL_I2CB

•

Input frequency ranges:

– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to

200MHz

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

– Crystal frequency range: 8MHz to 40MHz

OUT1B

DDO

OUT1

DDD

•

Output frequency ranges:

DDO

OUT2

OUT2B

DDO

OUT3

OUT3B

CLKIN

CLKINB

XOUT

XIN/REF

DDA

CLKSEL

24 23 22 21 20 19

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

EPAD

•

Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

10 11 12

24-pin VFQFPN

•

Redundant clock inputs with manual switchover

Programmable loop bandwidth

Programmable output to output skew

Programmable slew rate control

Programmable crystal load capacitance

Individual output enable/disable

Power-down mode

1.8V, 2.5V or 3.3V core V

DDD

, V

DDA

Available in 24-pin VFQFPN 4mm x 4mm package

-40° to +85°C industrial temperature operation

SEL1/SDA

SEL0/SCL

SD/OE

DDO

OUT4

IDT5P49V5901A REVISION D 10/21/14

OUT4B

IDT5P49V5901A DATASHEET

Functional Block Diagram

XIN/REF

XOUT

DDO

OUT1

FOD1

OUT1B

CLKIN

CLKINB

FOD2

OUT2B

CLKSEL

SD/OE

FOD3

SEL1/SDA

SEL0/SCL

OTP

and

Control Logic

DDO

OUT0_SEL_I2CB

DDO

OUT2

PLL

DDO

OUT3

OUT3B

DDO

OUT4

FOD4

OUT4B

DDA

DDD

Applications

•

Ethernet switch/router

PCI Express 1.0/2.0/3.0

Broadcast video/audio timing

Multi-function printer

Processor and FPGA clocking

Any-frequency clock conversion

MSAN/DSLAM/PON

Fiber Channel, SAN

Telecom line cards

1 GbE and 10 GbE

PROGRAMMABLE CLOCK GENERATOR

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

Table 1: Pin Descriptions

Number

Name

CLKIN

CLKINB

XOUT

XIN/REF

DDA

Input

Power

Type

Internal

Pull-down

Internal

Pull-down

Description

Differential clock input. Weak 100kohms internal pull-down.

Complementary differential clock input. Weak 100kohms internal pull-down.

Crystal Oscillator interface output.

Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure that

the input voltage is 1.2V max.Refer to the section “Overdriving the XIN/REF

Interface”.

Analog functions power supply pin.Connect to 1.8V to 3.3V. V

DDA

and V

DDD

should

have the same voltage applied.

Internal

Pull-down

Input clock select. Selects the active input reference source in manual switchover

mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I2C programming as shown in Table 4.

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for SD/OE

pin to be configured as SD. The SP bit (0x02) controls the polarity of the signal to be

either active HIGH or LOW only when pin is configured as OE (Default is active

LOW.) Weak internal pull down resistor. When configured as SD, device is shut

down, differential outputs are driven high/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs are disabled, the

outputs can be selected to be tri-stated or driven high/low, depending on the

programming bits as shown in the SD/OE Pin Function Truth table.

Configuration select pin, or I

C SDA input as selected by OUT0_SEL_I2CB. Weak

internal pull down resistor.

Configuration select pin, or I

C SCL input as selected by OUT0_SEL_I2CB. Weak

internal pull down resistor.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT4/OUT4B.

Output Clock 4. Please refer to the Output Drivers section for more details.

Complementary Output Clock 4. Please refer to the Output Drivers section for more

details.

Complementary Output Clock 3. Please refer to the Output Drivers section for more

details.

Output Clock 3. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT3/OUT3B.

Complementary Output Clock 2. Please refer to the Output Drivers section for more

details.

Output Clock 2. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT2/OUT2B.

Complementary Output Clock 1. Please refer to the Output Drivers section for more

details.

Output Clock 1. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT1/OUT1B.

CLKSEL

Input

SD/OE

Input

Internal

Pull-down

SEL1/SDA

SEL0/SCL

DDO

OUT4

OUT4B

OUT3B

OUT3

DDO

OUT2B

OUT2

DDO

OUT1B

OUT1

DDO

Input

Power

Output

Power

Output

Power

Output

Power

Internal

Pull-down

Internal

Pull-down

REVISION D 10/21/14

PROGRAMMABLE CLOCK GENERATOR

IDT5P49V5901A DATASHEET

Number

Name

DDD

DDO

Power

Type

Description

Digital functions power supply pin. Connect to 1.8 to 3.3V. V

DDA

and V

DDD

should

have the same voltage applied.

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage

levels for OUT0.

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8 and 9.

If a weak pull up (10kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9 will be

configured as hardware select pins, SEL1 and SEL0. If a weak pull down (10Kohms)

is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will act as the SDA

and SCL pins of an I

C interface. After power up, the pin acts as a LVCMOS

reference output.

Connect to ground pad.

OUT0_SEL_I2CB

Input/

Output

Internal

Pull-down

ePAD

GND

PROGRAMMABLE CLOCK GENERATOR

REVISION D 10/21/14

IDT5P49V5901A DATASHEET

PLL Features and Descriptions

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

IDT5P49V5901A supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The IDT5P49V5901A implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Table 4: Input Clock Select

Input clock select. Selects the active input reference source in

manual switchover mode.

0 = XIN/REF, XOUT (default)

1 = CLKIN, CLKINB

CLKSEL Polarity can be changed by I

C programming as

shown in the table below.

PRIMSRC

CLKSEL

Source

XIN/REF

CLKIN, CLKINB

XIN/REF

Table 2: Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Input Reference

Loop

Frequency–Fref Bandwidth Min Bandwidth Max

(MHz)

(kHz)

350

300

126

1000

PRIMSRC is bit 1 of Register 0x13.

Table 3: Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

REG0:7 Config

OUT0_SEL_I2CB SEL1 SEL0

Access

@ POR

Yes

I2C

defaults

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300nS

Rise/Fall time and only a single pin can be changed at a time.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

REVISION D 10/21/14

PROGRAMMABLE CLOCK GENERATOR

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5P49V5901A708NLGI Related Products

	5P49V5901A708NLGI	5P49V5901A710NLGI	5P49V5901A713NLGI	5P49V5901A680NLGI
Description	Clock Generator	Clock Generator	Clock Generator	Clock Generator
Is it Rohs certified?	conform to	conform to	conform to	conform to
Reach Compliance Code	compliant	compliant	compli	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
Peak Reflow Temperature (Celsius)	260	260	260	260
Maximum time at peak reflow temperature	30	30	30	30
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-

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