Intel
®
LXT971A Single-Port 10/100 Mbps
PHY Transceiver
Datasheet
The Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver (called hereafter the LXT971A
Transceiver) directly supports both 100BASE-TX and 10BASE-T applications. It provides a
Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers
(MACs). The LXT971A Transceiver is IEEE compliant, and provides a Low Voltage Positive
Emitter Coupled Logic (LVPECL) interface for use with 100BASE-FX fiber networks. (This
document also supports the Intel
®
LXT971 Transceiver.) The LXT971A Transceiver supports
full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT971A
Transceiver can be set using auto-negotiation, parallel detection, or manual control. The
LXT971A Transceiver is fabricated with an advanced CMOS process and requires only a single
2.53.3 V power supply.
Applications
■
■
Combination 10BASE-T/100BASE-TX
or
100BASE-FX
Network Interface Cards
(NICs)
Network printers
■
■
10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
Cable Modems and Set-Top Boxes
Product Features
■
■
■
■
■
■
■
■
3.3 V Operation
Low power consumption (300 mW typical)
Low-power “Sleep” mode
10BASE-T and 100BASE-TX using a
single RJ-45 connection
IEEE 802.3-compliant 10BASE-T or
100BASE-TX ports with integrated filters
Auto-negotiation and parallel detection
MII interface with extended register
capability
Robust baseline wander correction
■
■
■
■
■
Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
JTAG boundary scan
MDIO serial port or hardware pin
configurable
100BASE-FX fiber-optic capable
Integrated, programmable LED drivers
— 64-ball Plastic Ball Grid Array (PBGA)
or 64-pin Quad Flat Package (LQFP)
— LXT971ABC - Commercial (0
°
to 70
°
C ambient).
— LXT971ABE - Extended (-40
°
to
85
°
C ambient).
— LXT971ALC - Commercial (0
°
to
70
°
C ambient).
— LXT971ALE - Extended (-40
°
to
85
°
C ambient).
Document Number: 249414-003
Revision Date: 25-Oct-2005
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel® LXT971A Single-Port 10/100 Mbps PHY Transceiver may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation.
2
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Contents
1.0
Introduction to This Document ......................................................................................... 11
1.1
1.2
2.0
3.0
4.0
5.0
Document Overview ............................................................................................11
Related Documents............................................................................................. 11
Block Diagram for Intel
®
LXT971A Transceiver ............................................................... 12
Ball and Pin Assignments for Intel
®
LXT971A Transceiver.............................................. 13
Signal Descriptions for Intel
®
LXT971A Transceiver........................................................ 17
Functional Description...................................................................................................... 24
5.1
Device Overview .................................................................................................25
5.1.1 Comprehensive Functionality ................................................................. 25
5.1.2 Optimal Signal Processing Architecture ................................................. 25
Network Media / Protocol Support.......................................................................26
5.2.1 10/100 Network Interface .......................................................................26
5.2.2 MII Data Interface ................................................................................... 29
5.2.3 Configuration Management Interface ..................................................... 29
Operating Requirements .....................................................................................32
5.3.1 Power Requirements ..............................................................................32
5.3.2 Clock Requirements ............................................................................... 32
Initialization.......................................................................................................... 33
5.4.1 MDIO Control Mode and Hardware Control Mode .................................35
5.4.2 Reduced-Power Modes .......................................................................... 35
5.4.3 Reset for Intel
®
LXT971A Transceiver ................................................... 36
5.4.4 Hardware Configuration Settings ...........................................................37
Establishing Link .................................................................................................39
5.5.1 Auto-Negotiation.....................................................................................39
5.5.2 Parallel Detection ................................................................................... 40
MII Operation....................................................................................................... 41
5.6.1 MII Clocks............................................................................................... 42
5.6.2 Transmit Enable .....................................................................................43
5.6.3 Receive Data Valid ................................................................................. 43
5.6.4 Carrier Sense ......................................................................................... 44
5.6.5 Error Signals........................................................................................... 44
5.6.6 Collision .................................................................................................. 44
5.6.7 Loopback................................................................................................ 45
100 Mbps Operation ............................................................................................46
5.7.1 100BASE-X Network Operations ...........................................................46
5.7.2 Collision Indication ................................................................................. 49
5.7.3 100BASE-X Protocol Sublayer Operations ............................................ 50
10 Mbps Operation.............................................................................................. 55
5.8.1 10BASE-T Preamble Handling ............................................................... 55
5.8.2 10BASE-T Carrier Sense .......................................................................55
5.8.3 10BASE-T Dribble Bits ........................................................................... 55
5.8.4 10BASE-T Link Integrity Test ................................................................. 56
5.8.5 Link Failure ............................................................................................. 56
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
3
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
5.9
5.10
5.8.6 10BASE-T SQE (Heartbeat) .................................................................. 56
5.8.7 10BASE-T Jabber .................................................................................. 56
5.8.8 10BASE-T Polarity Correction................................................................ 56
Monitoring Operations ......................................................................................... 57
5.9.1 Monitoring Auto-Negotiation................................................................... 57
5.9.2 Monitoring Next Page Exchange............................................................ 57
5.9.3 LED Functions........................................................................................ 58
5.9.4 LED Pulse Stretching ............................................................................. 59
Boundary Scan (JTAG 1149.1) Functions .......................................................... 60
5.10.1 Boundary Scan Interface........................................................................ 60
5.10.2 State Machine ........................................................................................ 60
5.10.3 Instruction Register ................................................................................ 60
5.10.4 Boundary Scan Register ........................................................................ 61
5.10.5 Device ID Register ................................................................................. 61
6.0
Application Information..................................................................................................... 62
6.1
6.2
6.3
Magnetics Information ......................................................................................... 62
Typical Twisted-Pair Interface ............................................................................. 62
Fiber Interface ..................................................................................................... 66
7.0
Electrical Specifications ................................................................................................... 70
7.1
7.2
Electrical Parameters .......................................................................................... 70
Timing Diagrams ................................................................................................. 76
8.0
9.0
10.0
Register Definitions - IEEE Base Registers ..................................................................... 88
Register Definitions - Product-Specific Registers ............................................................ 96
Intel
®
LXT971A Transceiver Package Specifications .................................................... 105
10.1
Top Label Markings........................................................................................... 107
11.0
Product Ordering Information ......................................................................................... 109
4
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Figures
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46
47
Intel
®
LXT971A Transceiver Block Diagram ...................................................... 12
Ball Assignments for Intel
®
LXT971A Transceiver 64-Ball PBGA ...................... 13
Pins for Intel
®
LXT971A Transceiver 64-Pin LQFP Package ............................. 14
Management Interface Read Frame Structure ................................................... 30
Management Interface Write Frame Structure ................................................... 30
Intel
®
LXT971A Transceiver MII Interrupt Logic ................................................. 31
Initialization Sequence for Intel
®
LXT971A Transceiver ..................................... 34
Hardware Configuration Settings .......................................................................38
Intel
®
LXT971A Transceiver Link Establishment Overview ................................ 39
Clocking for 10BASE-T ...................................................................................... 42
Clocking for 100BASE-X .................................................................................... 42
Clocking for Link Down Clock Transition ............................................................ 43
Intel
®
LXT971A Transceiver Loopback Paths ....................................................45
100BASE-X Frame Format ................................................................................ 46
100BASE-TX Data Path .....................................................................................47
100BASE-TX Reception with No Errors ............................................................. 48
100BASE-TX Reception with Invalid Symbol ..................................................... 48
100BASE-TX Transmission with No Errors ........................................................ 49
100BASE-TX Transmission with Collision .......................................................... 49
Intel
®
LXT971A Transceiver Protocol Sublayers ................................................ 50
LED Pulse Stretching ......................................................................................... 59
Intel
®
LXT971A Transceiver Typical Twisted-Pair Interface - Switch.................. 63
Intel
®
LXT971A Transceiver Typical Twisted-Pair Interface - NIC ...................... 64
Intel
®
LXT971A Transceiver Typical Media Independent Interface.....................65
Typical Interface - Intel
®
LXT971ATransceiver to 3.3 V Fiber Transceiver......... 67
Typical Interface - Intel
®
LXT971A Transceiver to 5 V Fiber Transceiver........... 68
Typical Interface - Intel
®
LXT971A Transceiver to Triple PECL-to-PECL
Logic Translator.................................................................................................69
Intel
®
LXT971A Transceiver 100BASE-TX Receive Timing - 4B Mode ..............76
Intel
®
LXT971A Transceiver 100BASE-TX Transmit Timing - 4B Mode ............. 77
Intel
®
LXT971A Transceiver 100BASE-FX Receive Timing................................ 78
Intel
®
LXT971A Transceiver 100BASE-FX Transmit Timing............................... 79
Intel
®
LXT971A Transceiver 10BASE-T Receive Timing ................................... 80
Intel
®
LXT971A Transceiver 10BASE-T Transmit Timing .................................. 81
Intel
®
LXT971A Transceiver 10BASE-T Jabber and Unjabber Timing ..............82
Intel
®
LXT971A Transceiver 10BASE-T SQE (Heartbeat) Timing .....................83
Intel
®
LXT971A Transceiver Auto-Negotiation and Fast Link Pulse Timing........ 84
Intel
®
LXT971A Transceiver Fast Link Pulse Timing .......................................... 84
Intel
®
LXT971A Transceiver MDIO Input Timing................................................. 85
Intel
®
LXT971A Transceiver MDIO Output Timing .............................................. 85
Intel
®
LXT971A Transceiver Power-Up Timing ................................................... 86
Intel
®
LXT971A Transceiver RESET_L Pulse Width and Recovery Timing........ 87
PHY Identifier Bit Mapping ................................................................................. 91
Intel
®
LXT971A Transceiver PBGA Package Specification .............................. 105
Intel
®
LXT971A Transceiver LQFP Package Specifications ............................. 106
Sample LQFP Package - Intel
®
LXT971A Transceiver ..................................... 107
Sample Pb-Free (RoHS-Compliant) LQFP Package -
Intel
®
LXT971A Transceiver.............................................................................. 107
Sample TPBGA Package - Intel
®
LXT971A Transceiver .................................. 108
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
5
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