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MT47H256M4HQ-25EIT

Description
256MX4 DDR DRAM, 0.35ns, PBGA60, 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
Categorystorage    storage   
File Size9MB,129 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance  
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MT47H256M4HQ-25EIT Overview

256MX4 DDR DRAM, 0.35ns, PBGA60, 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60

MT47H256M4HQ-25EIT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeBGA
package instructionTFBGA,
Contacts60
Reach Compliance Codecompliant
access modeMULTI BANK PAGE BURST
Maximum access time0.35 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B60
JESD-609 codee1
length11.5 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals60
word count268435456 words
character code256000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256MX4
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.5 V
Nominal supply voltage (Vsup)1.55 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width8 mm
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Features
DDR2 SDRAM
MT47R256M4 – 32 Meg x 4 x 8 banks
MT47R128M8 – 16 Meg x 8 x 8 banks
MT47R64M16 – 8 Meg x 16 x 8 banks
Features
V
DD
/V
DDQ
= +1.55V, 1.5–1.9V range
Backward compatible with 1.8V DDR2
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1
t
CK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS compliant
Supports JEDEC clock jitter specification
Very low power operation
Options
1
Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks)
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
FBGA package (Pb-free) – x16
84-ball FBGA (8mm x 12.5mm) Rev. G
FBGA package (Pb-free) – x4, x8
60-ball FBGA (8mm x 11.5mm) Rev. G
Timing – cycle time
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 4 (DDR2-667)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Operating temperature
Commercial (0°C
T
C
85°C)
Industrial (–40°C
T
C
95°C;
–40°C
T
A
85°C)
Automotive (–40°C
T
C
, T
A
105ºC)
Revision
Note:
Marking
256M4
128M8
64M16
HR
HQ
-25E
-25
-3E
-3
-37E
None
IT
AT
:G
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on
www.micron.com
for
product offerings and availability.
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed Grade
-25E
-25
-3E
-3
-37E
CL = 3
400
400
400
400
400
CL = 4
533
533
667
533
533
CL = 5
800
667
667
667
n/a
CL = 6
800
800
n/a
n/a
n/a
CL = 7
n/a
n/a
n/a
n/a
n/a
t
RC
(ns)
55
55
54
55
55
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2009
Micron Technology, Inc. All rights reserved.

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