W27E257
32K
×
8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27E257 is a high-speed, low-power Electrically Erasable and Programmable Read Only
Memory organized as 32768
×
8 bits that operates on a single 5 volt power supply. The W27E257
provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the
W27E256.
FEATURES
•
High speed access time:
•
•
•
•
100/120/150 nS (max.)
Read operating current: 15 mA (typ.)
Erase/Programming operating current
1 mA (typ.)
Standby current: 5
µA
(typ.)
Single 5V power supply
•
+14V erase/+12V programming voltage
•
Fully static operation
•
All inputs and outputs directly TTL/CMOS
compatible
•
Three-state outputs
•
Available packages: 28-pin 600 mil DIP and
32-pin PLCC
PIN CONFIGURATIONS
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
BLOCK DIAGRAM
Q0
.
.
Q7
CE
OE
CONTROL
OUTPUT
BUFFER
A0
.
.
A14
VCC
GND
VPP
DECODER
CORE
ARRAY
A V
V A A
A 1 P N C 1 1
7 2 P C C 4 3
4 3 2 1 3 3 3
2 1 0 29
5
28
6
27
7
26
8
32-pin
25
PLCC
9
24
10
23
11
12 1 1 1 1 1 1 2 22
13 4 5 6 7 8 9 0 21
Q Q G N
1 2 N C
D
Q Q Q
3 4 5
PIN DESCRIPTION
A8
A9
A11
NC
OE
A10
CE
Q7
Q6
A6
A5
A4
A3
A2
A1
A0
NC
Q0
SYMBOL
A0−A14
Q0−Q7
CE
OE
V
PP
V
CC
GND
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
Publication Release Date: January 1997
Revision A3
-1-
W27E257
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27E257 has two control functions, both of which produce data
at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (T
ACC
) is equal to the delay from CE to output
(T
CE
), and data are available at the outputs T
OE
after the falling edge of OE, if T
ACC
and T
CE
timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E257 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
Erase mode is entered when V
PP
is raised to V
PE
(14V), V
CC
= V
CE
(5V), OE = V
IH
(2V or above but
lower than V
CC
), A9 = V
HH
(14V), A0 = V
IL
(0.8V or below but higher than GND), and all other
address pins equal V
IL
and data input pins equal V
IH
. Pulsing CE low starts the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if V
PP
= V
PE
(14V), CE = V
IH
, and OE =
V
IL
.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when V
PP
is raised to V
PP
(12V), V
CC
= V
CP
(5V), OE = V
IH
, the address pins equal the desired address, and the input pins
equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully
programmed with the desired data. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
program margin. This mode will be entered after the program operation if V
PP
= V
PP
(12V), CE = V
IH
,
and OE = V
IL
.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When CE = V
IH
, erasing or programming of non-target chips is inhibited, so that except for the
CE and OE pins, the W27E257 may have common inputs.
-2-
W27E257
Standby Mode
The standby mode significantly reduces V
CC
current. This mode is entered when CE = V
IH
. In
standby mode, all outputs are in a high impedance state, independent of OE.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27E257 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power
dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
interested in three supply current issues: standby current levels (I
SB
), active current levels (I
CC
), and
transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1
µ
F ceramic capacitor connected between its V
CC
and GND. This high frequency, low inherent-
inductance capacitor should be placed as close as possible to the device. Additionally, for every eight
devices, a 4.7
µF
electrolytic capacitor should be placed at the array's power supply connection
between V
CC
and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace
inductances.
TABLE OF OPERATING MODES
(V
PP
= 12V, V
PE
= 14V, V
HH
= 12V, V
CP
= 5V, X = V
IH
or V
IL
)
MODE
CE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Program Inhibit
Erase
Erase Verify
Erase Inhibit
Product Identifier-manufacturer
Product Identifier-device
V
IL
V
IL
V
IH
V
CC
±0.3V
V
IL
V
IH
V
IH
V
IL
V
IH
V
IH
V
IL
V
IL
OE
V
IL
V
IH
X
X
V
IH
V
IL
V
IH
V
IH
V
IL
V
IH
V
IL
V
IL
A0
X
X
X
X
X
X
X
V
IL
X
X
V
IL
V
IH
PINS
A9
X
X
X
X
X
X
X
V
PE
X
X
V
HH
V
HH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CP
V
CP
V
CP
V
CC
V
CC
V
CP
V
CC
V
CC
V
PP
V
CC
V
CC
V
CC
V
CC
V
PP
V
PP
V
PP
V
PE
V
PE
V
PP
V
CC
V
CC
OUTPUTS
D
OUT
High Z
High Z
High Z
D
IN
D
OUT
High Z
D
IH
D
OUT
High Z
DA (Hex)
02 (Hex)
-3-
Publication Release Date: January 1997
Revision A3
W27E257
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Ambient Temperature with Power Applied
Storage Temperature
Voltage on all pins with Respect to Ground Except V
PP,
A9
and V
CC
pins
Voltage on V
PP
Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground
Voltage on V
CC
Pin with Respect to Ground
RATING
-55 to +125
-65 to +125
-0.5 to V
CC
+0.5
-0.5 to +14.5
-0.5 to +14.5
-0.5 to +7
UNIT
°C
°C
V
V
V
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC Erase Characteristics
(T
A
= 25° C
±5°
C, V
CC
= 5.0V
±10%)
PARAMETER
Input Load Current
V
CC
Erase Current
V
PP
Erase Current
Input Low Voltage
Input High Voltage
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Erase Voltage
V
PP
Erase Voltage
V
CC
Supply Voltage (Erase)
SYM.
I
LI
I
CP
I
PP
V
IL
V
IH
V
OL
V
OH
V
ID
V
PE
V
CE
CONDITIONS
MIN.
V
IN
= V
IL
or V
IH
CE = V
IL
CE = V
IL
-
-
I
OL
= 2.1 mA
I
OH
= -0.4 mA
-
-
-
-10
-
-
-0.3
2.4
-
2.4
13.75
13.75
4.5
LIMITS
TYP.
-
-
-
-
-
-
-
14
14
5.0
MAX.
10
30
30
0.8
5.5
0.45
-
14.25
14.25
5.5
UNIT
µA
mA
mA
V
V
V
-
V
V
V
Note: V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
.
CAPACITANCE
(V
CC
= 5V, T
A
= 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
C
IN
C
OUT
CONDITIONS
V
IN
= 0V
V
OUT
= 0V
MAX.
6
12
UNIT
pF
pF
-4-
W27E257
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
0.45V to 2.4V
10 nS
0.8V/2.0V
C
L
= 100 pF, I
OH
/I
OL
= -0.4 mA/2.1 mA
CONDITIONS
AC Test Load and Waveform
+1.3V
(IN914)
3.3K ohm
D
OUT
100 pF (Including Jig and Scope)
Input
Test Points
2.4V
0.45V
2.0V
0.8V
Output
Test Points
2.0V
0.8V
-5-
Publication Release Date: January 1997
Revision A3