D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
Aa
FEATURES
Low Cost 3.3 V-CMOS Mixed-Signal Front End (MxFE™)
Converter for Broadband Modems
10-/12-Bit D/A Converter (TxDAC+
®
)
64/32 MSPS Input Word Rate
2 /4 Interpolating LPF or BPF Transmit Filter
128 MSPS DAC Output Update Rate
Wide (26 MHz) Transmit Bandwidth
Power-Down Mode
10-/12-Bit, 50 MSPS A/D Converter
Fourth Order Low-Pass Filter 12 MHz or 26 MHz
with Bypass
–6 dB to +36 dB Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Clock Outputs
Voltage Regulator Controller
48-Lead LQFP Package
APPLICATIONS
Powerline Networking
Home Phone Networking
xDSL
Broadband Wireless
Home RF
PRODUCT DESCRIPTION
PWR DN
Tx QUIET
GAIN
Tx [5:0]
Tx SYNC
Broadband Modem
Mixed-Signal Front End
AD9875
FUNCTIONAL BLOCK DIAGRAM
AD9875
Tx
MUX
10
Kx INTERPOLATION
LPF/BPF
10
TxDAC+
Tx+
Tx–
PLL-A
L
CLK-A
CLOCK GEN
CLK-B
Rx SYNC
PLL-B
M/N
V
REF
VRC
GATE
FB
OSCIN
XTAL
Rx [5:0]
Rx
MUX
10
ADC
PGA
LPF
PGA
Rx+
Rx–
SPORT
3
REGISTER
CONTROL
The AD9875 is a single-supply broadband modem mixed-
signal front end (MxFE) IC. The devices contain a transmit
path Interpolation Filter and DAC, and a receive path PGA,
LPF, and ADC supporting a variety of broadband modem
applications. Also on chip is a PLL clock multiplier that pro-
vides all required clocks from a single crystal or clock input.
The AD9875 provides 10-bit converter performance on both
the Tx and Rx paths.
The TxDAC+ uses a selectable digital 2× or 4× interpolation
low-pass or band-pass filter to further oversample transmit
data and reduce the complexity of analog reconstruction filtering.
The transmit path signal bandwidth can be as high as 26 MHz
at an input data rate of 64 MSPS. The 10-bit DAC provides
differential current outputs for optimum noise and distortion
performance. The DAC full-scale current can be adjusted
from 2 mA to 20 mA by a single resistor, providing 20 dB of
additional gain range.
The receive path consists of a PGA, LPF, and ADC. The two-stage
PGA has a gain range of –6 dB to +36 dB, and is programmable
in 2 dB steps, adding 42 dB of dynamic range to the receive path.
The receive path LPF cutoff frequency can be programmed to either
12 MHz or 26 MHz. The filter cutoff frequency can also be tuned
or bypassed where filter requirements differ. The 10-bit ADC
uses a multistage differential pipeline architecture to achieve
excellent dynamic performance with low power consumption.
The AD9875 provides a voltage regulator controller (VRC) that
can be used with an external power MOSFET transistor to form
a cost-effective 1.3 V linear regulator.
The digital transmit and receive ports are each multiplexed to a
bus width of 5/6 bits and are clocked at a frequency of twice the
10-bit word rate.
The AD9875 ADC and/or DAC can also be used at higher
sampling rates as high as 64 MSPS in a 5-bit resolution non-
multiplexed mode.
The AD9875 is pin compatible with the 12-bit AD9876. Both are
available in a space-saving 48-lead LQFP package. They are specified
over the industrial (–40°C to +85°C) temperature range.
MxFE is a trademark of Analog Devices, Inc.
TxDAC+ is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9875–SPECIFICATIONS
Parameter
OSC IN CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
CLOCK OUTPUT CHARACTERISTICS
CLKA Jitter (f
CLKA
Derived from PLL)
CLKA Duty Cycle
CLKB Jitter (f
CLKB
Derived from PLL)
CLKB Duty Cycle
Tx CHARACTERISTICS
Tx Path Latency, 4× Interpolation
Interpolation Filter Bandwidth (–0.1 dB)
4× Interpolation, LPF
2× Interpolation, LPF
TxDAC
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
10 MHz Analog Out AD9875 (20 MHz BW)
Wideband SFDR (to Nyquist, 64 MHz Max)
5 MHz Analog Out
10 MHz Analog Out
Narrowband SFDR (3 MHz Window)
10 MHz Analog Out
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)
Rx PATH CHARACTERISTICS
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
DC Accuracy
Differential Nonlinearity
Integral Nonlinearity
Dynamic Performance
(A
IN
= –0.5 dBFS, f = 5 MHz)
@ f
OSCIN
= 32 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
Dynamic Performance
(A
IN
= –0.5 dBFS, f = 10 MHz)
@ F
PLLB/2
= 50 MHz
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
(V
S
= 3.3 V 10%, f
OSCIN
= 32 MHz, f
DAC
= 128 MHz, Gain = –6 dB, R
SET
= 4.02 k ,
100 DAC single-ended load, unless otherwise noted.)
Test
Level
II
II
III
III
III
III
III
III
II
II
II
II
II
II
II
II
II
III
III
III
III
I
III
III
III
III
III
II
II
II
II
II
Temp
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
Min
10
40
Typ
Max
64
60
Unit
MHz
%
pF
MΩ
ps rms
%
ps rms
%
f
DAC
Cycles
MHz
MHz
Bits
MHz
mA
V
% FS
µA
LSB
LSB
pF
dBc/Hz
dB
dBc
dBc
dBc
dBFS
Bits
MHz
Cycles
LSB
LSB
50
3
100
14
50
±
5
33
50
±
5
82
13
26
10
10
2
–0.5
–5
0
10
±
2
7
0.5
5
–90
128
20
+1.5
+5
19
1
59
61
78
72
80
–76
10
7.5
5.5
–1.0
–2.0
±
0.25
±
0.5
55
+1.0
+2.0
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
59.6
9.5
60
–65
68
dB
Bits
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
–2–
54
8.6
55
–61
68
dB
Bits
dB
dB
dB
REV. A
AD9875
Parameter
Rx PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain
(12 MHz Filter)
(26 MHz Filter)
Gain Step Size
Gain Step Accuracy
Gain Range Error
Offset Error, PGA Gain = 0 dB (AD9875)
Absolute Gain Error, PGA Gain = 0 dB
Rx PATH INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB)
Input Referred Noise (at +36 dB Gain with Filter)
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Rx PATH LPF (Low Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 22 MHz
Passband Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH LPF (High Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 44 MHz
Passband Ripple
Group Delay Variation
Settling Time
(to 1% FS, Min to Max Gain Change)
Total Harmonic Distortion at Max Gain (THD)
Rx PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)
Roll-Off in Stopband
–3 dB Frequency
Rx PATH DISTORTION PERFORMANCE
IMD: f1 = 6.9 MHz, f2 = 7.1 MHz
12 MHz Filter: 0 dB
: 30 dB
28 MHz Filter: 0 dB
: 30 dB
POWER-DOWN/DISABLE TIMING
Power-Up Delay (Power-Down-to-Active)
DAC
PLL
ADC
PGA
LPF
Interpolator
VRC
Minimum RESET Pulsewidth Low (t
RL
)
DAC I
OUT
Off after Tx QUIET Asserted
DAC I
OUT
On after Tx QUIET Deasserted
Power-Down Delay (Active-to-Power-Down)
DAC
Interpolator
REV. A
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Test
Level
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
III
II
II
II
Min
Typ
–6
36
30
2
±
0.4
±
1.0
±
4.0
±
0.8
4
4
270
50
16
684
40
12
±
7
20
±
1.0
30
150
–68
26
±
7
20
±
1.2
15
80
–65
1
6
f
ADC
/400
Max
Unit
dB
dB
dB
dB
dB
dB
LSB
dB
Vppd
pF
Ω
MHz
µV
rms
µV
rms
dB
MHz
%
dB
dB
ns
ns
dBc
MHz
%
dB
dB
ns
ns
dBc
Cycle
dB/Octave
Hz
25°C
25°C
25°C
25°C
III
III
III
III
–65
–57
–65
–56
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
II
II
II
II
II
II
II
III
II
II
II
II
–3–
40
10
1000
1
1
200
2
5
200
1
400
200
µs
µs
µs
µs
µs
ns
µs
f
OSCIN
Cycle
ns
µs
ns
ns
AD9875–SPECIFICATIONS
(continued)
Parameter
Tx PATH INTERFACE
Maximum Input Nibble Rate, 2× Interpolation
Tx-Set Up Time (t
SU
)
Tx-Hold Time (t
HD
)
Rx PATH INTERFACE
Maximum Output Nibble Rate
Rx-DataValid Time (t
VT
)
Rx-Data Hold Time (t
HT
)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Digital Output Rise/Fall Time
POWER SUPPLY
All Blocks Powered Up
I
S_TOTAL
(Total Supply Current)
I
S_TOTAL
(Tx_QUIET Pin Asserted)
Digital Supply Current (I
DRVDD
+ I
DVDD
)
Analog Supply Current (I
AVDD
)
Power Consumption of Functional Blocks
Rx LPF
ADC and FPGA
Rx Reference
Interpolator
DAC
PLL-B
PLL-A
Voltage Regulator Controller
All Blocks Powered Down
Supply Current I
S
, f
OSCIN
= 32 MHz
Supply Current I
S
, f
OSCIN
Idle
Power Supply Rejection
Tx Path (∆V
S
= 10%)
Rx Path (∆V
S
= 10%)
SERIAL CONTROL BUS
Maximum SCLK Frequency (f
SCLK
)
Clock Pulsewidth High (t
PWH
)
Clock Pulsewidth Low (t
PWL
)
Clock Rise/Fall Time
Data/Chip-Select Setup Time (t
DS
)
Data Hold Time (t
DH
)
Data Valid Time (t
DV
)
RECEIVE-TO-TRANSMIT ISOLATION
(10 MHz, Full-Scale Sinewave Output/Output)
Isolation: Tx Path to Rx Path, Gain = +36 dB
Isolation: Rx Path to Tx Path, Gain = –6 dB
VOLTAGE REGULATOR CONTROLLER
Output Voltage (V
FB
with SI2301 Connected)
Line Regulation (∆V
FB%
/∆V
DVDD%
×
100%)
Load Regulation (∆V
FB
/∆I
LOAD
)
Maximum Load Current (I
LOAD
)
Specifications subject to change without notice.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Test
Level
II
II
II
I
II
II
II
II
II
II
III
II
II
II
Min
128
3.0
0
110
Typ
Max
Unit
MHz
ns
ns
MHz
ns
ns
V
V
µA
µA
µF
V
V
ns
3.0
1.5
V
DRVDD
– 0.7
0.4
12
12
3
V
DRVDD
– 0.6
1.5
0.4
2.5
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
I
III
III
III
III
III
III
III
III
III
III
III
II
II
III
III
II
II
II
II
II
II
II
25
18
18
262
172
77
185
110
55
2
33
18
8
24
1
19
10
62
54
288
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
22
12
mA
mA
dB
dB
MHz
ns
ns
ms
ns
ns
ns
1
25
0
20
25°C
25°C
Full
25°C
25°C
Full
III
III
I
III
III
II
–4–
1.25
–75
–70
1.30
100
60
1.35
dB
dB
V
%
mΩ
mA
REV. A
250
京公网安备 11010802033920号
EEWORLD
