DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= No Connect
2
Resistor Nonlinearity
R-INL
R
WB
, V
A
= No Connect
R
AB
T
A
= 25°C, Model: AD840XYY10
Nominal Resistance
3
Resistance Tempco
∆R
AB
/∆T
V
AB
= V
DD
, Wiper = No Connect
I
W
= 1 V/R
Wiper Resistance
R
W
Nominal Resistance Match
∆R/R
AB
CH 1 to 2, 3, or 4, V
AB
= V
DD
, T
A
= 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
Integral Nonlinearity
4
INL
4
Differential Nonlinearity
DNL
V
DD
= 5 V
DNL
V
DD
= 3 V T
A
= 25°C
DNL
V
DD
= 3 V T
A
= –40°C, +85°C
Code = 80
H
Voltage Divider Tempco
∆V
W
/∆T
Full-Scale Error
V
WFSE
Code = FF
H
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Current
7
Shutdown Wiper Resistance
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
8
Power Dissipation (CMOS)
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
Range
I
DD
I
DD
P
DISS
PSS
PSS
BW_10K
THD
W
t
S
e
NWB
C
T
8
–2
–1
–1
–1.5
–4
0
0
±
1/2
±
1/4
±
1/4
±
1/2
15
–2.8
1.3
+2
+1
+1
+1.5
0
2
V
DD
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
R
L
= 2.2 kΩ to V
DD
I
OL
= 1.6 mA, V
DD
= 5 V
V
IN
= 0 V or +5 V, V
DD
= 5 V
2.4
75
120
0.01
100
5
200
0.8
2.1
0.6
V
DD
– 0.1
0.4
±
1
5
2.7
5.5
5
4
27.5
0.001
0.03
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
R = 10 kΩ
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
R
WB
= 5 kΩ, f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
0.01
0.9
0.0002
0.006
600
0.003
2
9
–65
NOTES
11
Typicals represent average readings at 25°C and V
DD
= 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1
I
W
= 50
µA
for V
DD
= 3 V and I
W
= 400
µA
for V
DD
= 5 V for the 10 kΩ versions.
13
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
14
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
1
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I
DD
versus logic voltage.
19
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= 5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
–2–
REV. C
AD8400/AD8402/AD8403
SPECIFICATIONS
(V
Parameter
DD
=3V
10% or 5 V
10%, V
A
= V
DD
, V
B
= 0 V, –40 C
≤
T
A
≤
+125 C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS–50 k
Symbol
and 100 k
VERSIONS
Min
–1
–2
35
70
Typ
1
±
1/4
±
1/2
50
100
500
53
0.2
Max
+1
+2
65
130
100
1
Unit
LSB
LSB
kΩ
kΩ
ppm/°C
Ω
%
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= No Connect
Resistor Nonlinearity
2
R-INL
R
WB
, V
A
= No Connect
R
AB
T
A
= 25°C, Model: AD840XYY50
Nominal Resistance
3
T
A
= 25°C, Model: AD840XYY100
R
AB
Resistance Tempco
∆R
AB
/∆T
V
AB
= V
DD
, Wiper = No Connect
Wiper Resistance
R
W
I
W
= 1 V/R
Nominal Resistance Match
∆R/R
AB
CH 1 to 2, 3, or 4, V
AB
= V
DD
, T
A
= 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs)
Resolution
N
4
Integral Nonlinearity
INL
DNL
V
DD
= 5 V
Differential Nonlinearity
4
DNL
V
DD
= 3 V T
A
= 25°C
DNL
V
DD
= 3 V T
A
= –40°C, +85°C
Voltage Divider Tempco
∆V
W
/∆T
Code = 80
H
Full-Scale Error
V
WFSE
Code = FF
H
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Current
7
Shutdown Wiper Resistance
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
8
Power Dissipation (CMOS)
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
Range
I
DD
I
DD
P
DISS
PSS
PSS
BW_50K
BW_100K
THD
W
t
S
_50K
t
S
_100K
e
NWB
_50K
e
NWB
_100K
C
T
8
–4
–1
–1
–1.5
–1
0
0
±
1
±
1/4
±
1/4
±
1/2
15
–0.25
+0.1
+4
+1
+1
+1.5
0
+1
V
DD
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
R
L
= 2.2 kΩ to V
DD
I
OL
= 1.6 mA, V
DD
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
2.4
15
80
0.01
100
5
200
0.8
2.1
0.6
V
DD
– 0.1
0.4
±
1
5
2.7
5.5
5
4
27.5
0.001
0.03
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
V
DD
= 5 V
±
10%
V
DD
= 3 V
±
10%
R = 50 kΩ
R = 100 kΩ
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
R
WB
= 25 kΩ, f = 1 kHz,
RS
= 0
R
WB
= 50 kΩ, f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
0.01
0.9
0.0002
0.006
125
71
0.003
9
18
20
29
–65
NOTES
11
Typicals represent average readings at 25°C and V
DD
= 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See TPC 29 test circuit.
1
I
W
= V
DD
/R for V
DD
= 3 V or 5 V for the 50 kΩ and 100 kΩ versions.
13
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
14
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
1
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
1
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I
DD
versus logic voltage.
19
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All Dynamic Characteristics use V
DD
= 5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
Specifications subject to change without notice.
REV. C
–3–
AD8400/AD8402/AD8403–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS–1 k
Parameter
Symbol
(V
DD
= 3 V 10% or 5 V 10%, V
A
= V
DD
, V
B
= 0 V,
–40 C
≤
T
A
≤
+125 C unless otherwise noted.)
VERSION
Min
–5
–4
0.8
Typ
1
–1
±
1.5
1.2
700
53
0.75
Max
+3
+4
1.6
100
2
Unit
LSB
LSB
kΩ
ppm/°C
Ω
%
Bits
LSB
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
%
µs
nV/√Hz
dB
Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= No Connect
2
Resistor Nonlinearity
R-INL
R
WB
, V
A
= No Connect
Nominal Resistance
3
R
AB
T
A
= 25°C, Model: AD840XYY1
V
AB
= V
DD
, Wiper = No Connect
Resistance Tempco
∆R
AB
/∆T
Wiper Resistance
R
W
I
W
= 1 V/R
AB
Nominal Resistance Match
∆R/R
AB
CH 1 to 2, V
AB
= V
DD
, T
A
= 25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
Resolution
N
INL
Integral Nonlinearity
4
Differential Nonlinearity
4
DNL
V
DD
= 5 V
DNL
V
DD
= 3 V, T
A
= 25°C
Voltage Divider Temperature Coefficent
∆V
W
/∆T
Code = 80
H
Code = FF
H
Full-Scale Error
V
WFSE
Zero-Scale Error
V
WZSE
Code = 00
H
RESISTOR TERMINALS
Voltage Range
5
Capacitance
6
Ax, Bx
Capacitance
6
Wx
Shutdown Supply Current
7
Shutdown Wiper Resistance
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
8
Power Dissipation (CMOS)
9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage
Crosstalk
11
V
A, B, W
C
A, B
C
W
I
A_SD
R
W_SD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
IL
C
IL
V
DD
Range
I
DD
I
DD
P
DISS
PSS
PSS
BW_1K
THD
W
t
S
e
NWB
C
T
8
–6
–4
–5
–20
0
0
±
2
–1.5
–2
25
–12
6
+6
+2
+5
0
10
V
DD
f = 1 MHz, Measured to GND, Code = 80
H
f = 1 MHz, Measured to GND, Code = 80
H
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0
V
A
= V
DD
, V
B
= 0 V,
SHDN
= 0, V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
R
L
= 2.2 kΩ to V
DD
I
OL
= 1.6 mA, V
DD
= 5 V
V
IN
= 0 V or 5 V, V
DD
= 5 V
2.4
75
120
0.01
50
5
100
0.8
2.1
0.6
V
DD
– 0.1
0.4
±
1
5
2.7
5.5
5
4
27.5
0.008
0.13
V
IH
= V
DD
or V
IL
= 0 V
V
IH
= 2.4 V or 0.8 V, V
DD
= 5.5 V
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= 5.5 V
∆V
DD
= 5 V
±
10%
∆V
DD
= 3 V
±
10%
R = 1 kΩ
V
A
= 1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
V
A
= V
DD
, V
B
= 0 V,
±
1% Error Band
R
WB
= 500
Ω,
f = 1 kHz,
RS
= 0
V
A
= V
DD
, V
B
= 0 V
0.01
0.9
0.0035
0.05
5,000
0.015
0.5
3
–65
NOTES
11
Typicals represent average readings at 25°C and V
DD
= 5 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
1
positions. R-DNL measures the relative step change from ideal between successive tap positions. See TPC 29 test circuit.
1
I
W
= 500
µA
for V
DD
= 3 V and I
W
= 2.5 mA for V
DD
= 5 V for 1 kΩ version.
13
V
AB
= V
DD
, Wiper (V
W
) = No Connect.
14
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL Specification limits of
±
1 LSB maximum are Guaranteed Monotonic operating conditions. See TPC 28 test circuit.
15
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
16
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
17
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
18
Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See TPC 20 for a plot of I
DD
versus logic voltage.
19
P
DISS
is calculated from (I
DD
×
V
DD
). CMOS logic level inputs result in minimum power dissipation.
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