PCMCIA Flash Memory Card
FLD Series
PCMCIA Flash Memory Card
General Description
4 MEGABYTE through 40 MEGABYTE (AMD based)
Features
•
Low cost High Density Linear Flash Card
•
Supports 5V only systems
•Based
on AMD Flash Components
-low standby power without entering reset mode
-allows standard access from standby mode
•Fast
Read Performance
- 150ns Maximum Access Time
•
x8/ x16 Data Interface
•
High Performance Random Writes
- 7µs typical Word Write Time
•
Automated Write and Erase Algorithms
- AMD Command Set
•
1 000,000 Erase Cycles per Block
•
64K word (128kB) symmetrical Block Architecture
•
PC Card Standard Type I Form Factor
WEDC’s PCMCIA Flash memory cards offer high
density linear Flash solid state storage solutions for
code and data storage, high performance disk
emulation and execute in place (XIP) applications in
mobile PC and dedicated (embedded) equipment.
Packaged in a PCMCIA type I housing, each card
contains a connector, an array of Flash memories
packaged in TSOP packages and card control logic.
The card control logic provides the system interface
and controls the internal Flash memories. Combined
with file management software, such as Flash
Translation Layer (FTL), WEDC Flash cards provide
removable high-performance disk emulation.
The WEDC FLD series is based on AMD Flash
memories. The FLD series offers byte wide and word
wide operation, low power modes and Card
Information Structure (CIS) for easy identification of
card characteristics.
Note: Standard options include attribute memory.
Cards without attribute memory are available. Cards
are also available with or without a hardware write
protect switch.
Architecture Overview
WEDC’s FLD series is designed to support from two to twenty (see Block diagram) 16Mb components, providing
a wide range of density options. Cards are based on the Am29F017 (16Mb) device for 5V only applications. The
device code for the Am29F017 is 3Dh and the manufacturer’s ID is 01h. This card is compatible with D series
cards from AMD. Cards utilizing 16Mb components provide densities ranging from 4MB to 40MB in 4MB
increments.
In support of the PC Card (PCMCIA) standard for word wide access, devices are paired. Therefore, the Flash
array is structured in 64K word (128kB)blocks. Write, read operations can be performed as either a word or byte
wide operation. By multiplexing A0, CE1# and CE2#, 8-bit hosts can access all data on data lines DQ0 - DQ7. The
FLD series cards conform with the PC Card Standard (formerly PCMCIA) and supported JEIDA, providing
electrical and physical compatibility. The PC Card form factor offers an industry standard pinout and mechanical
outline, allowing density upgrades without system design changes.
WEDC’s standard cards are shipped with WEDC’s silkscreen design. Cards are also available with blank housings
(no silkscreen). The blank housings are available in both a recessed (for label) and flat housing. Please contact your
WEDC sales representative for further information on Custom artwork.
PC Card Products
White Electronic Designs
One Research Drive Westborough, MA 01581
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July 28. 1999
1
FLD series
Block Diagram
Device type Manuf ID Device ID
Am29F017
01
H
3D
H
Device Pair (N/2 - 1)
Device (N-1)
Device (N-2)
CSn
Array
Address
Bus
ADDRESS
BUFFER
ADDRESS BUS
A1-A25
Control
Address
Bus
M Res
WL#
RL#
WH#
RH#
CSn
Device 3
Device 2
CS1
CS0
Q2
Q0
Ctrl
At/Reg enable
REG#
A0
WP
Control Logic
PCMCIA Interface
Qn
WE#
OE#
CE2#
CE1#
Device Pair 1
Device Pair 0
Device 1
Device 0
CS0
Vcc
WH# RH#
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
WL# RL#
0000h
attrib. mem
CIS
EEPROM 2kB
Vcc
control
Q0-Q7
Vcc
I/O buffer
DATA
BUS
D8-D15
DATA
BUS
D0-D7
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July 28. 1999
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FLD series
Pinout
Pin Signal name I/O
Function
Active
Pin Signal name I/O
Function
Active
1
GND
Ground
35
GND
Ground
2
DQ3
I/O
Data bit 3
36
CD1#
O
Card Detect 1
LOW
3
DQ4
I/O
Data bit 4
37
DQ11
I/O
Data bit 11
4
DQ5
I/O
Data bit 5
38
DQ12
I/O
Data bit 12
5
DQ6
I/O
Data bit 6
39
DQ13
I/O
Data bit 13
6
DQ7
I/O
Data bit 7
40
DQ14
I/O
Data bit 14
7
CE1#
I
Card enable 1 LOW
41
DQ15
I
Data bit 15
8
A10
I
Address bit 10
42
CE2#
I
Card Enable 2
LOW
9
OE#
I
Output enable LOW
43
VS1
O
Voltage Sense 1
N.C.
10
A11
I
Address bit 11
44
RFU
Reserved
11
A9
I
Address bit 9
45
RFU
Reserved
12
A8
I
Address bit 8
46
A17
I
Address bit 17
13
A13
I
Address bit 13
47
A18
I
Address bit 18
14
A14
I
Address bit 14
48
A19
I
Address bit 19
2MB(3)
15
WE#
I
Write Enable LOW
49
A20
I
Address bit 20
4MB(3)
16
RDY/BSY# O
Ready/Busy
LOW
50
A21
I
Address bit 21
17
Vcc
Supply Voltage
51
Vcc
Supply Voltage
18
Vpp1
Prog. Voltage N.C.
52
Vpp2
Prog. Voltage
N.C.
8MB(3)
19
A16
I
Address bit 16
53
A22
I
Address bit 22
16MB(3)
20
A15
I
Address bit 15
54
A23
I
Address bit 23
32MB(3)
21
A12
I
Address bit 12
55
A24
I
Address bit 24
64MB(3)
22
A7
I
Address bit 7
56
A25
I
Address bit 25
23
A6
I
Address bit 6
57
VS2
O
Voltage Sense 2
N.C.
24
A5
I
Address bit 5
58
RST
I
Card Reset
HIGH
25
A4
I
Address bit 4
59
Wait#
O Extended Bus cycle
LOW(2)
26
A3
I
Address bit 3
60
RFU
Reserved
27
A2
I
Address bit 2
61
REG#
I
Attrib Mem Select
28
A1
I
Address bit 1
62
BVD2
O Bat. Volt. Detect 2
(2)
29
A0
I
Address bit 0
63
BVD1
O Bat. Volt. Detect 1
(2)
30
DQ0
I/O
Data bit 0
64
DQ8
I/O
Data bit 8
31
DQ1
I/O
Data bit 1
65
DQ9
I/O
Data bit 9
32
DQ2
I/O
Data bit 2
66
DQ10
O
Data bit 10
33
WP
O
Write Potect HIGH
67
CD2#
O
Card Detect 2
LOW
34
GND
Ground
68
GND
Ground
Notes:
1) RDY/BSY is an open drain output, external pull-up resistor is required
2) Wait#, BVD1 and BVD2 are driven high for compatibility
3) Shows density for which specified address bit is MSB. Higher order address bits are no connects (ie 4MB A21 is MSB A22 - A25 are NC).
Mechanical
.063
3.370
.039
2.126
.039
.400
.130
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3
FLD series
Card Signal Description
Symbol
A0 - A25
Type
INPUT
Name and Function
ADDRESS INPUTS:
A0 through A25 enable direct addressing of
up to 64MB of memory on the card. Signal A0 is not used in word
access mode. A25 is the most significant bit
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the
bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2#
enables odd byte accesses. Multiplexing A0, CE1# and CE2# allows
8-bit hosts to access all data on DQ0 - DQ7.
OUTPUT ENABLE:
Active low signal gating read data from the
memory card.
WRITE ENABLE:
Active low signal gating write data to the
memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase
or program algorithms. A high output indicates that the card is ready
to accept accesses. A low output indicates that one or more devices
in the memory card are busy with internally timed erase or write
activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These
signals are connected to ground internally on the memory card. The
host socket interface circuitry shall supply 10K-ohm or larger pull-up
resistors on these signal pins.
WRITE PROTECT:
Write protect reflects the status of the Write
Protect switch on the memory card. WP set to high = write protected,
providing internal hardware write lockout to the Flash array.
If card does not include optional write protect switch, this signal will
be pulled low internally indicating write protect = "off".
PROGRAM/ERASE POWER SUPPLY:
Not connected for 5V
only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry.
GROUND:
for all internal circuitry.
ATTRIBUTE MEMORY SELECT :
provides access to Flash
memory card registers and Card Information Structure in the
Attribute Memory Plane.
RESET:
Active high signal for placing card in Power-on default
state. Reset can be used as a Power-Down signal for the memory
array.
WAIT:
This signal is pulled high internally for compatibility. No
wait states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to
maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card's VCC
requirements. VS1 and VS2 are open to indicate a 5V card has been
inserted.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven
or left floating
DQ0 - DQ15
CE1#, CE2#
INPUT/OUTPUT
INPUT
OE#
WE#
RDY/BSY#
INPUT
INPUT
OUTPUT
CD1#, CD2#
OUTPUT
WP
OUTPUT
VPP1, VPP2
VCC
GND
REG#
N.C.
INPUT
RST
INPUT
WAIT#
BVD1, BVD2
VS1, VS2
OUTPUT
OUTPUT
OUTPUT
RFU
N.C.
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4
FLD series
Absolute Maximum Ratings (2)
Operating Temperature TA (ambient)
Commercial
Industrial
Storage Temperature
Commercial
Industrial
Voltage on any pin relative to V
SS
V
CC
supply Voltage relative to V
SS
** Advanced information
DC Characteristics
(1)
Sym
I
CCR
I
CCW
I
CCE
I
CCS
(CMOS)
Parameter
V
CC
Read Current
V
CC
Program Current
V
CC
Erase Current
V
CC
Standby Current
Density
(Mbytes)
All
All
All
2MB
(4MB)
2,3
80
Notes
Typ
(4)
Max
75
150
150
230
Notes:
(1) During transitions, inputs may undershoot to -
2.0V or overshoot to V
CC
+2.0V for periods less than
20ns.
(2) Stress greater than those listed under “Absolute
Maximum ratings” may cause permanent damage to
the device. This is a stress rating only and
functional operation at these or any other conditions
greater than those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
0°C to +60 °C
-40°C to +85 °C **
-30°C to +80 °C
-40°C to +85 °C **
-0.5V to V
CC
+0.5V (1)
-0.5V to +7.0V
Units
mA
mA
mA
µA
Test Conditions
V
CC
= V
CC
max
tcycle = 150ns,CMOS levels
V
CC
= V
CC
max
Control Signals = V
CC
Reset = V
SS
, CMOS levels
CMOS Test Conditions: V
CC
= 5V ± 5%, VIL = V
SS
± 0.2V, VIH = V
CC
± 0.2V
Notes:
1. All currents are RMS values unless otherwise specified. ICCR, ICCW and ICCE are based on Word wide operations
2. Control Signals: CE
1
#, CE
2
#, OE#, WE#, REG#
3. ICCD and ICCS are specified for lowest density card for each component type (2MB for 8Mb components and 4MB for 16Mb
components) This represents a single pair of devices. For higher densities multiply the number of device pairs by the specified current in
the table. For example a 40MB card will use 10 device pairs of 16Mb components. The maximum ICCD will be 10 x 40µA = 400µA. The
maximum ICCS will be 10 x 230µA = 2.3mA.
4. Typical: V
CC
= 5V, T = +25°C
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
V
LKO
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
Erase/Program
Lock Voltage
Notes
1
1
1
1
1
1
1
Min
Max
±20
±20
Units
µA
µA
V
V
V
V
V
Test Conditions
V
CC
= V
CC
MAX
Vin =V
CC
or V
SS
V
CC
= V
CC
MAX
Vout =V
CC
or V
SS
0
0.7V
CC
V
CC
-0.4
2.0
0.8
V
CC
+0.5
0.4
V
CC
IOL = 3.2mA
IOH = -2.0mA
Notes:
1) Values are the same for byte and word wide modes for all card densities.
2) Exceptions: Leakage currents on CE1#, CE2#, OE#, REG# and WE# will be < 500 µA when VIN = GND due to
internal pull-up resistors. Leakage currents on RST will be <150µA when VIN=V
C C
due to internal pull-down resistor
PC Card Products
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One Research Drive Westborough, MA 01581
http://www.whiteedc.com
July 28. 1999
5
FLD series
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