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TSXPC603EVA5ML

Description
RISC Microprocessor, 32-Bit, 133MHz, CMOS, CQFP240, CERAMIC, LCC-240
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size632KB,38 Pages
Manufacturere2v technologies
Download Datasheet Parametric View All

TSXPC603EVA5ML Overview

RISC Microprocessor, 32-Bit, 133MHz, CMOS, CQFP240, CERAMIC, LCC-240

TSXPC603EVA5ML Parametric

Parameter NameAttribute value
Makere2v technologies
Parts packaging codeQFP
package instruction,
Contacts240
Reach Compliance Codeunknown
ECCN code3A001.A.3
Address bus width32
bit size32
boundary scanYES
maximum clock frequency66.67 MHz
External data bus width64
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeS-CQFP-G240
low power modeYES
Number of terminals240
Package body materialCERAMIC, METAL-SEALED COFIRED
Package shapeSQUARE
Package formFLATPACK
Certification statusNot Qualified
speed133 MHz
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Terminal formGULL WING
Terminal locationQUAD
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
TSPC603E
PowerPC 603e™ RISC MICROPROCESSOR Family
PID6-603e Specification
DESCRIPTION
The PID6-603e implementation of PC603e (after named 603e)
is a low-power implementation of reduced instruction set com-
puter (RISC) microprocessors PowerPC™ family. The 603e
implements 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603e is a low-power 3.3-volt design and provides four soft-
ware controllable power-saving modes.
The 603e is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions
can execute out of order for increased performance ; however,
the 603e makes completion appear sequential. The 603e inte-
grates five execution units and is able to execute five instruc-
tions in parallel.
The 603e provides independent on-chip, 16-Kbyte, four-way
set-associative, physically addressed caches for instructions
and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers
that provide support for demand-paged virtual memory
address translation and variable-sized block translation.
The 603e has a selectable 32 or 64-bit data bus and a 32-bit
address bus. The 603e interface protocol allows multiple mas-
ters to complete for system resources through a central exter-
nal arbiter. The 603e supports single-beat and burst data
transfers for memory accesses, and supports memory-
mapped I/O.
The 603e uses an advanced, 3.3-V CMOS process technology
and maintains full interface compatibility with TTL devices.
The 603e integrates in system testability and debugging fea-
tures through JTAG boundary-scan capability.
CERQUAD 240
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
MAIN FEATURES
H
2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)
H
Superscalar (3 instructions per clock peak).
H
Dual 16KB caches.
H
Selectable bus clock.
H
32-bit compatibility PowerPC implementation.
H
On chip debug support.
H
P
D
typical = 3.2 Watts (100 MHz), full operating conditions.
H
Nap, doze and sleep modes for power savings.
H
Branch folding.
H
64-bit data bus (32-bit data bus option).
H
4-Gbyte direct addressing range.
H
Pipelined single/double precision float unit.
H
H
H
H
IEEE 754 compatible FPU.
IEEE P 1149-1 test mode (JTAG/C0P).
f
int
max = 100/120/133 MHz.
f
bus
max = 66 MHz.
Compatible CMOS input
TTL Output.
G suffix
CBGA 255
Ceramic Ball Grid Array
SCREENING / QUALITY / PACKAGING
This product is manufactured in full compliance with :
H
MIL-STD-883 class B or According to TCS standards
H
Upscreenings based upon TCS standards
H
Full military temperature range (T
c
= -55°C, T
c
= +125°C)
Industrial temperature range (T
c
=
40°C, T
c
= +110°C)
H
V
CC
= 3.3 V
±
5 %.
H
240 pin Cerquad or 255 pin CBGA packages
December1998
1/38

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