16 Megabit FLASH EEPROM
DP5Z2MX8PAnY
PRELIMINARY
DESCRIPTION:
The DP5Z2MX8PAnY “SLCC” devices are a revolutionary new memory
subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC). Available unleaded, straight leaded, “J” leaded, gullwing
leaded packages, or mounted on a 50-pin PGA co-fired ceramic substrate.
The Device packs 16-Megabits of FLASH EEPROM in an area as small as
0.463 in2 while maintaining a total height as low as 0.171 inches.
The DP5Z2MX8PAnY is a 2 Meg x 8 FLASH EEPROM based memory module.
Each SLCC is hermetically sealed making the module suitable for commercial,
industrial and military applications.
By using SLCCs, the “Stack” family of modules offer a higher board density
of memory than available with conventional through-hole, surface mount or
hybrid techniques.
DP5Z2MX8PAY3
DP5Z2MX8PAH3
FEATURES:
•
Organization: 2 Meg x 8
•
Fast Access Times: 70*, 90, 120, 150ns (max.)
* V
DD
= 5.0V
±
5%
•
Single 5.0 Volt Power Supply
•
High-Density Symmetrically Blocked Architecture
- 32 Uniform Sectors of 64 Kbytes Each
•
Extended Cycling Capability
- 100,000 Write/Erase Cycles per Sector
•
Automated Erase and Program Cycles
- Command User Interface
- Status Register
DP5Z2MX8PAJ3
•
SRAM-Compatible Write Interface
•
Hardware Data Protection Feature
•
Packages Available:
DP5Z2MX8PAY
DP5Z2MX8PAIY
DP5Z2MX8PAHY
DP5Z2MX8PAJY
DP5Z2MX8PAA3
- Erase / Write Lockout during Power Transitions
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin Gullwing Leaded SLCC
48 - Pin J Leaded SLCC
50 - Pin PGA Dense-SLCC
DP5Z2MX8PAA3
DP5Z2MX8PAI3
30A161-A1
Rev. A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to
c
hange or discontinue information on this product without prior notice.
1
DP5Z2MX8PAn3
PRELIMINARY
Dense-Pac Microsystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
A0 - A20
I/O0 - I/O7
CE
WE
OE
RESET
RY/BY
V
DD
V
SS
N.C.
PIN NAMES
Address
Data Inputs/Outputs
Chip Enable
Write Enable
Output Enable
Hardware reset Pin, Active Low
Ready/Busy Output
Single Power (+5.0V)
Ground
No Connect
PIN-OUT DIAGRAM
48 - PIN SLCC
48 - PIN STRAIGHT LEADED SLCC
48 - PIN GULLWING LEADED SLCC
48 - PIN J LEADED SLCC
48 - PIN PGA DENSE-SLCC
50 - PIN PGA
DENSE-STACK
2
30A161-A1
Rev. A
Dense-Pac Microsystems, Inc.
PRELIMINARY
DP5Z2MX8PAn3
BUS OPERATION
This section describes the requirements and use of the device
bus operations, which are initiated through the internal
command register. The command register itself does not occupy
any addressable memory locations. The register is composed of
latches that store the commands, along with the address and data
information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The
state machine outputs dictate the function of the device. The
appropriate device bus operations table lists the inputs and
control levels required, and the resulting output. The following
subsections describe each of these operations in further detail.
Table 1.
Device Bus Operation
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect (See Note)
Legend:
L = Logic LOW = V
IL
H = Logic HIGH = V
IH
,
CE
L
L
V
DD
±
0.5V
H
L
X
X
V
ID
= 12.0±0.5V,
OE
L
H
X
X
H
X
X
WE
H
L
X
X
H
X
X
RESET
H
H
V
DD
±
0.5V
H
H
L
V
ID
D
IN
= Data In,
A0 - A20
A
IN
A
IN
X
X
X
X
A
IN
I/O0 - I/O7
D
OUT
D
IN
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
D
IN
X = Don’t Care,
D
OUT
= Data Out,
A
IN
= Address In
To read array data from the outputs, the system must drive the
CE and OE pins to V
IL
. CE is the power control and selects the
device. OE is the output control and gates array data to the output
pins. WE should remain at V
IH
.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to
obtain array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC
Read Operations table for timing specifications and to the Read
Operations Timings diagram for the timing waveforms. I
CC1
in
the DC Characteristics table represents the active current
specification for reading array data.
To write a command or command sequence (which includes
programming data to the device and erasing sectors of memory),
the system must drive WE and CE to V
IL
, and OE to V
IH
.
Requirements for Reading Array Data
An erase operation can erase one sector, multiple sectors, or the
entire device. The Sector Address Tables indicate the address
space that each sector occupies. A “Sector Address” consists of
the address bits required to uniquely select a sector. See the
“Command Definitions” section for details on erasing a sector or
the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on I/O7-I/O0. Standard read cycle
timings apply in this mode. Refer to the “Autoselect Mode” and
“Autoselect Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the active current
specification for the write mode. The “AC Characteristics”
section contains timing specification tables and timing diagrams
for write operations.
During an erase or program operation, the system may check the
status of the operation by reading the status bits on I/O7-I/O0.
Standard read cycle timings and I
CC
read specifications apply.
Refer to “Write Operation Status” for more information, and to
each AC Characteristics section for timing diagrams.
Program and Erase Operation Status
Writing Commands/Command Sequences
30A161-A1
Rev. A
3
DP5Z2MX8PAn3
PRELIMINARY
Standby Mode
Dense-Pac Microsystems, Inc.
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
The device enters the CMOS standby mode when CE and RESET
pins are both held at V
DD
0.5 V. (Note that this is a more
restricted voltage range than V
IH
.) The device enters the TTL
standby mode when CE and RESET pins are both held at V
IH
.
The device requires standard access time (t
CE
) for read access
when the device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the RESET pin is
driven low. Refer to the next section, “RESET: Hardware Reset
Pin”.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
In the DC Characteristics tables, I
SB1
and I
SB2
represent the
standby current specification.
The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the RESET
pin low for at least a period of t
RP
, the device
immediately
terminates
any operation in progress, tristates all data output
pins, and ignores all read/write attempts for the duration of the
RESET pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted should
be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When
RESET is held at V
IL
, the device enters the TTL standby mode; if
RESET is held at V
SS
±
0.5V, the device enters the CMOS standby
mode.
The RESET pin may be tied to the system reset circuitry. A system
reset would thus also reset the Flash memory, enabling the system
to read the boot-up firmware from the Flash memory.
If RESET is asserted during a program or erase operation, the
RY/BY pin remains a “0" (busy) until the internal reset operation
is complete, which requires a time of t
READY
(during Embedded
Algorithms). The system can thus monitor RY/BY to determine
whether the reset operation is complete. If RESET is asserted
when a program or erase operation is not executing (RY/BY pin
is ”1"), the reset operation is completed within a time of t
READY
(not during Embedded Algorithms). The system can read data
t
RH
after the RESET pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET parameters and
timing diagram.
When the OE input is at V
IH
, output from the device is disabled.
The output pins are placed in the high impedance state.
RESET: Hardware Reset Pin
Output Disable Mode
Autoselect Mode
The autoselect mode provides manufacturer and device
identification through identifier codes output on I/O7-I/O0. This
mode is primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the autoselect
codes can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode
requires V
ID
(11.5V to 12.5V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 2, Autoselect Codes
(High Voltage Method). The “Command Definitions”, table 4,
shows the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming
equipment may then read the corresponding identifier code on
I/O7-I/O0.
To access the autoselect codes in-system, the host system can
issue the autoselect command via the command register, as
shown in the “Command Definitions” table. This method does
not require V
ID
. See Command Definitions for details on using
the autoselect mode.
Table 2. Auto Select Codes
(High Voltage Method)
Description
Manufacture ID
Device ID
CE
L
L
OE
L
L
WE
H
H
A20-A18 A17-A10
X
X
X
X
A9
V
ID
V
ID
A8-A7
X
X
A6
V
IL
V
IL
A5-A2
X
X
A1
V
IL
V
IL
A0
V
IL
V
IH
I/O7-I/O0
01h
ADh
L = Logic Low = V
IL
, H = Logic High = V
IH
,
SA = Sector Address,
X = Don’t Care.
4
30A161-A1
Rev. A
Dense-Pac Microsystems, Inc.
PRELIMINARY
DP5Z2MX8PAn3
Table 3: SECTOR ADDRESS
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
A20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A18
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Address Range
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
NOTE:
All sectors are 64 Kbytes in size.
30A161-A1
Rev. A
5
Embedded System
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