FEMTOCLOCK™ CRYSTAL-TO-
LVDS/LVCMOS CLOCK GENERATOR
ICS8402010I
G
ENERAL
D
ESCRIPTION
ICS8402010I is a low phase noise Clock Generator
and is a member of the HiperClockS™ family of high
HiPerClockS™
performance clock solutions from IDT. The device
provides three banks of outputs and a reference
clock. Each bank can be independently enabled by
using output enable pins. A 25MHz, 18pF parallel resonant
crystal is used to generate the 16.66MHz, 62.5MHz and 25MHz
frequencies. The typical RMS phase jitter for this device is less
than 1ps.
F
EATURES
•
Three banks of outputs:
Bank A/B: three single-ended LVCMOS outputs at 16.66MHz
Bank C: three differential LVDS outputs at 62.5MHz
One single-ended reference clock output at 25MHz
•
Crystal input frequency: 25MHz
•
Maximum output frequency: 62.5MHz
•
RMS phase jitter @ 62.5MHz, using a 25MHz crystal,
Integration Range (1.875MHz - 20MHz): 0.375ps (typical)
•
Full 3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
IC
S
B
LOCK
D
IAGRAM
OE[2:0]
Pullup
3
LVCMOS - 16.66MHz
QA0
QA1
QA2
25MHz
÷30
P
IN
A
SSIGNMENT
XTAL_OUT
XTAL_IN
XTAL_IN
LVCMOS - 16.66MHz
OSC
V
DDA
OE2
OE1
OE0
GND
GND
XTAL_OUT
Phase
Detector
VCO
500MHz
QB0
QB1
QB2
÷30
32 31 30 29 28 27 26 25
V
DDO
_
REF
REF_OUT
GND
GND
QA0
QA1
QA2
V
DDO
_
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
V
DDO
_
C
nQC2
QC2
nQC1
QC1
nQC0
QC0
V
DDO
_
C
÷20
ICS8402010I
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
LVDS 62.5MHz
22
21
20
19
18
17
QC0
nQC0
÷8
QC1
nQC1
QC2
nQC2
LVCMOS - 25MHz
QB0
QB1
QB2
GND
MR
V
DDO
_
B
GND
V
DD
REF_OUT
IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR
1
ICS8402010AKI REV. A AUGUST 28, 2008
ICS8402010I
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4, 13,
16, 25, 32
5, 6, 7
8
9
10, 11, 12
14
15
17, 24
18, 19
20, 21
22, 23
26
Name
V
DDO_REF
REF_OUT
GND
QA0, QA1, QA2
V
DDO_A
V
DDO_B
QB0, QB1, QB2
MR
V
DD
V
DDO_C
QC0, nQC0
QC1, nQC1
QC2, nQC2
V
DDA
Power
Output
Power
Output
Power
Power
Output
Input
Power
Power
Output
Output
Output
Power
Type
Description
Output power supply pin for REF_OUT output.
Single-ended reference clock output. LVCMOS/LVTTL interface
levels.
Power supply ground.
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
Output power supply pin for Bank A LVCMOS outputs.
Output power supply pin for Bank B LVCMOS outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Master reset, resets the internal dividers. During reset, LVCMOS
outputs are pulled LOW and LVDS outputs are pulled LOW and
Pulldown
HIGH, (QCx pulled LOW, nQCx pulled HIGH).
LVCMOS/LVTTL interface levels.
Core supply pin.
Output power supply pin for Bank C LVDS outputs.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Analog supply pin.
Output enable pins. See Table 3. LVCMOS/LVTTL interface levels.
27, 28, 29 OE0, OE1, OE2
Input
Pullup
30,
XTAL_IN,
Cr ystal oscillator interface. XTAL_OUT is the output.
Input
31
XTAL_OUT
XTAL_IN is the input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QA[0:2],
QB[0:2],
REF_OUT
QA[0:2],
QB[0:2],
REF_OUT
V
DD
, V
DDO_A
= V
DDO_B
=
V
DDO_REF
= 3.465V
Test Conditions
Minimum
Typical
4
15
51
51
20
Maximum
Units
pF
pF
kΩ
kΩ
Ω
T
ABLE
3. OE F
UNCTION
T
ABLE
Inputs
OE2
X
X
X
X
0
1
OE1
X
X
0
1
X
X
OE0
0
1
X
X
X
X
Output States
QA0, QB0, QC0 disabled
QA0, QB0, QC0 enabled
QA1, QB1, QC1 disabled
QA1, QB1, QC1 enabled
QA2, QB2, QC2 disabled
QA2, QB2, QC2 enabled
IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR
2
ICS8402010AKI REV. A AUGUST 28, 2008
ICS8402010I
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS, V
DDO_C
)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
Junction-to-Ambient
Package Thermal Impedance,
θ
JB
Junction-to-Board
Package Thermal Impedance,
θ
JC
Junction-to-Case
10mA
15mA
-40°C to +85°C
-65°C to 150°C
37.0°C/W (0 mps)
0.5°C/W
29.6°C/W
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO_A, _B
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO_A
= V
DDO_B
= V
DDO_REF
= V
DDO_C
= 3.3V ± 5%,T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B,
V
DDO_C,
V
DDO_REF
I
DD
I
DDA
I
DDO_A
+ I
DDO_B
+
I
DDO_C
+ I
DDO_REF
Parameter
Core Supply Voltage
Analog Supply Voltage
Test Conditions
Minimum
3.135
V
DD
– 0.15
3.135
Typical
3.3
3.3
Maximum
3.465
V
DD
3.465
Units
V
V
Output Supply Voltage
3.3V
V
Power Supply Current
Analog Supply Current
Output Supply Current
25
15
30
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO_A
= V
DDO_B
= V
DDO_REF
= 3.3V ± 5%,T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
Output
High Voltage; NOTE 1
OE0, OE1, OE2
MR
OE0, OE1, OE2
MR
REF_OUT,
QA[0:2], QB[0:2]
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO_X
= 3.465V
-150
-5
2.6
0.5
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
Output
REF_OUT,
V
DDO_X
= 3.465V
Low Voltage; NOTE 1 QA[0:2], QB[0:2]
NOTE: V
DDO_X
denotes V
DDO_A,
V
DDO_B
and V
DDO_REF.
NOTE 1: Outputs terminated with 50
Ω
to V
DDO_A, _B, _REF
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR
3
ICS8402010AKI REV. A AUGUST 28, 2008
ICS8402010I
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO_C
= 3.3V ± 5%,T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.325
1.450
Test Conditions
Minimum
300
Typical
450
Maximum
550
50
1.575
50
Units
mV
mV
V
mV
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO_A
= V
DDO_B
= V
DDO_REF
= V
DDO_C
= 3.3V ± 5%,T
A
= -40°C
TO
85°C
Symbol
Parameter
QC[0:2]/
nQC[0:2]
REF_OUT
QA[0:2],
QB[0:2]
QA[0:2],
QB[0:2]
QC[0:2]/
nQC[0:2]
QA[0:2]
Test Conditions
Minimum
Typical
62.5
25
16.66
125
60
100
125
Maximum
Units
MH z
MHz
MHz
ps
ps
ps
ps
ps
450
1000
53
55
ps
ps
%
%
f
OUT
Output Frequency
t
sk(o)
Output Skew;
NOTE 1, 2
Bank Skew;
NOTE 2, 3
t
sk(b)
QB[0:2]
RMS Phase Jitter
QC[0:2]/
62.5MHz, Integration Range:
t
jit(Ø)
0.375
(Random); NOTE 4
nQC[0:2]
1.875MHz – 20MHz
QC[0:2]/
20% to 80%
165
nQC[0:2]
Output
t
R
/ t
F
Rise/Fall Time
QA[0:2],
20% to 80%
450
QB[0:2]
QC[0:2]/
47
nQC[0:2]
odc
Output Duty Cycle
QA[0:2],
45
QB[0:2]
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO_X
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: Please refer to the Phase Noise Plot.
IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR
4
ICS8402010AKI REV. A AUGUST 28, 2008
ICS8402010I
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS CLOCK GENERATOR
T
YPICAL
P
HASE
N
OISE AT
62.5MH
Z
(
LVDS
)
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.375ps (typical)
➤
Ethernet Filter
Phase Noise Result by adding
Ethernet Filter to raw data
O
FFSET
F
REQUENCY
(H
Z
)
5
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
IDT
™
/ ICS
™
LVDS/LVCMOS CLOCK GENERATOR
➤
ICS8402010AKI REV. A AUGUST 28, 2008
➤
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