LS5912C
MONOLITHIC DUAL
N-CHANNEL JFET
Linear Systems replaces discontinued Siliconix & National 2N5912C
The LS5912C are monolithic dual JFETs. The
monolithic dual chip design reduces parasitics and
gives better performance at very high frequencies while
ensuring extremely tight matching. These devices are
an excellent choice for use as wideband differential
amplifiers in demanding test and measurement
applications. The LS5912C is a direct replacement for
discontinued Siliconix and National LS5912C.
The 8 Pin P-DIP provides ease of manufacturing, and
the symmetrical pinout prevents improper orientation.
(See Packaging Information).
FEATURES
Improved Direct Replacement for SILICONIX & NATIONAL 2N5912C
LOW NOISE (10KHz)
e
n
~ 4nV/√Hz
HIGH TRANSCONDUCTANCE (100MHz)
g
fs
≥ 4000µS
1
ABSOLUTE MAXIMUM RATINGS
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Power Dissipation
Continuous Power Dissipation (Total)
Maximum Currents
Gate Current
Maximum Voltages
Gate to Drain
Gate to Source
MIN
‐‐
‐‐
0.95
‐‐
TYP
‐‐
‐‐
‐‐
MAX
40
40
1
UNITS
mV
µV/°C
%
‐65°C to +150°C
‐55°C to +135°C
500mW
50mA
‐25V
‐25V
CONDITIONS
V
DG
= 10V, I
D
= 5mA
V
DG
= 10V, I
D
= 5mA
T
A
= ‐55°C to +125°C
V
DS
= 10V, V
GS
= 0V
LS5912C Applications:
Wideband Differential Amps
High-Speed,Temp-Compensated Single-
Ended Input Amps
High-Speed Comparators
Impedance Converters and vibrations
detectors
.
MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)
SYMBOL
CHARACTERISTIC
|V
GS1
– V
GS2
|
Differential Gate to Source Cutoff Voltage
∆|V
GS1
– V
GS2
| / ∆T
Differential Gate to Source Cutoff
Voltage Change with Temperature
I
DSS1
/ I
DSS2
Gate to Source Saturation Current Ratio
|I
G1
– I
G2
|
Differential Gate Current
g
fs1
/ g
fs2
CMRR
Click To Buy
‐‐
20
1
nA
%
Forward Transconductance Ratio
2
Common Mode Rejection Ratio
0.95
‐‐
‐‐
85
‐‐
dB
TYP.
‐‐
‐‐
0.7
‐‐
‐‐
‐1
‐1
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
7
4
MAX.
‐5
‐‐
‐4
40
‐50
‐50
10000
10000
100
150
5
1.2
1
20
10
UNITS
V
mA
pA
µS
pF
dB
nV/√Hz
CONDITIONS
I
G
= ‐1µA, V
DS
= 0V
V
DS
= 10V, I
D
= 1nA
I
G
= 1mA, V
DS
= 0V
V
DG
= 10V, I
G
= 5mA
V
DS
= 10V, V
GS
= 0V
V
GS
= ‐15V, V
DS
= 0V
V
DG
= 10V, I
D
= 5mA
V
DG
= 10V, I
D
= 5mA
Forward Transconductance
Output Conductance
Input Capacitance
Reverse Transfer Capacitance
Noise Figure
Equivalent Input Noise Voltage
4000
4000
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
V
DG
= 10V, I
D
= 5mA
T
A
= +125°C
V
DS
= 10V, I
D
= 5mA, f = 1kHz
V
DG
= 5V to 10V, I
D
= 5mA
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV
GSS
Gate to Source Breakdown Voltage
‐25
V
GS(off)
Gate to Source Cutoff Voltage
‐1
V
GS(F)
Gate to Source Forward Voltage
‐‐
V
GS
Gate to Source Voltage
‐0.3
3
I
DSS
Gate to Source Saturation Current
7
3
I
GSS
Gate Leakage Current
‐‐
I
G
Gate Operating Current
‐‐
g
fs
g
os
C
ISS
C
RSS
NF
e
n
V
DG
= 10V, I
D
= 5mA, f = 1MHz
V
DG
= 10V, I
D
= 5mA, f = 10kHz, R
G
= 100KΩ
V
DG
= 10V, I
D
= 5mA, f = 100Hz
V
DG
= 10V, I
D
= 5mA, f = 10kHz
Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired
2. Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3%
3. Assumes smaller value in numerator
Available Packages:
Please contact Micross for full package and die dimensions:
Email:
chipcomponents@micross.com
Web:
www.micross.com/distribution.aspx
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
LS5912C in PDIP
LS5912C available as bare die
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