simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
AC performance includes 73.1dB SNR and 88dB spurious
free dynamic range (SFDR). Low power consumption per
channel reduces heat in high channel count applications.
Integrated bypass capacitance and flow-through pinout
reduces overall board space requirements.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.2LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode).
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
8-Channel Simultaneous Sampling ADC
73.1dB SNR
88dB SFDR
Low Power: 140mW/113mW/94mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Internal Bypass Capacitance, No External
Components
140-Pin (9mm × 11.25mm) BGA Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
Typical applicaTion
1.8V
V
DD
CHANNEL 1
ANALOG
INPUT
CHANNEL 2
ANALOG
INPUT
S/H
14-BIT
ADC CORE
14-BIT
ADC CORE
1.8V
OV
DD
OUT1A
OUT1B
OUT2A
DATA
SERIALIZER
14-BIT
ADC CORE
OUT2B
SERIALIZED
LVDS
OUTPUTS
LTM9011-14, 125Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
AMPLITUDE (dBFS)
–30
–40
–50
–60
–70
–80
S/H
•••
•••
•••
CHANNEL 8
ANALOG
INPUT
ENCODE
INPUT
S/H
OUT8A
OUT8B
DATA
CLOCK
OUT
FRAME
•••
–90
–100
–110
–120
PLL
0
10
GND
OGND
9009101114 TA01
20
30
40
FREQUENCY (MHz)
50
60
9009101114 TA01b
9009101114p
1
LTM9011-14/
LTM9010-14/LTM9009-14
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTion
TOP VIEW
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN–
,
PAR/SER, SENSE) (Note 3) ...........–0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTM9011C, 9010C, 9009C ....................... 0°C to 70°C
LTM9011I, 9010I, 9009I ...................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1
2
3
4
5
6
7
8
9
10
BGA PACKAGE
140-LEAD (11.25mm × 9.00mm × 2.72mm)
T
JMAX
= 150°C,
θ
JA
= 28°C/W
orDer inForMaTion
LEAD FREE FINISH
LTM9011CY-14#PBF
LTM9011IY-14#PBF
LTM9010CY-14#PBF
LTM9010IY-14#PBF
LTM9009CY-14#PBF
LTM9009IY-14#PBF
TRAY
LTM9011CY-14#PBF
LTM9011IY-14#PBF
LTM9010CY-14#PBF
LTM9010IY-14#PBF
LTM9009CY-14#PBF
LTM9009IY-14#PBF
PART MARKING*
LTM9011Y14
LTM9011Y14
LTM9010Y14
LTM9010Y14
LTM9009Y14
LTM9009Y14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to:
http://www.linear.com/packaging/
9009101114p
2
LTM9011-14/
LTM9010-14/LTM9009-14
converTer characTerisTics
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
LTM9011-14
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
External Reference
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
MIN
14
–4.1
–0.9
–12
–2.6
±1.2
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
4.1
0.9
12
0
TYP
MAX
14
LTM9010-14
MIN
–3.25
–0.8
–12
–2.6
TYP
±1
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
MAX
3.25
0.8
12
0
14
LTM9009-14
MIN
–2.75
–0.8
–12
–2.6
TYP
±1
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
MAX
2.75
0.8
12
0
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
Differential Analog Input (Note 6)
l
l
l
l
analog inpuT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
,
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
l
l
MIN
V
CM
– 100mV
0.625
TYP
1 to 2
V
CM
1.250
155
130
100
MAX
V
CM
+ 100mV
1.300
UNITS
V
P-P
V
V
µA
µA
µA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
External Voltage Reference Applied to SENSE External Reference Mode
Analog Input Leakage Current No Encode
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1
–3
–6
0
0.15
80
1
3
6
µA
µA
µA
ns
ps
RMS
dB
MHz
Figure 6 Test Circuit
800
9009101114p
3
LTM9011-14/
LTM9010-14/LTM9009-14
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTM9011-14
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
l
DynaMic accuracy
LTM9010-14
MIN
70.7
TYP
73
72.9
72.6
88
85
82
90
90
90
73
72.6
72
–90
–105
MAX
LTM9009-14
MIN
70.9
TYP
73
72.9
72.5
88
85
82
90
90
90
72.9
72.6
72
–90
–105
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
MIN
71.1
TYP
73.1
73
72.6
88
85
82
90
90
90
73
72.6
72
–90
–105
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
75
75
77
l
84
84
85
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
Crosstalk, Near Channel
Crosstalk, Far Channel
5MHz Input
70MHz Input
140MHz Input
10MHz Input (Note 12)
10MHz Input (Note 12)
l
69.6
70.2
70.4
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
9009101114p
4
LTM9011-14/
LTM9010-14/LTM9009-14
DigiTal inpuTs anD ouTpuTs
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
V
OD
V
OS
R
TERM
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 8)
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
l
l
l
0.2
1.1
0.2
10
3.5
1.2
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
V
0.6
V
µA
pF
Ω
10
3
µA
pF
454
250
1.375
1.375
mV
mV
V
V
Ω
10
3
3.6
30
3.5
Single-Ended Encode Mode (ENC
–
Tied to GND)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
l
l
l
1.2
0
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
l
l
l
1.3
–10
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
【AT-START-F425 Review】Bootloader - Learning and Information Search
1. First consult the chip manual4K bytes of boot program memory is used as a boot loader ( Bootloader ), which can be configured as a...
Source: https://arstechnica.com/gadgets/2020/12/google-kills-android-things-its-iot-os-in-january/Google promised three years of updates at launch, but stopped updating after a year.Google's latest di...
There are several well-known methods for dealing with supply voltage reversals. The most obvious method is to connect a diode between the source and the load, but this results in additional power diss...
Asus P552SJ laptop, as shown below, has two hard disks: Disk 0 and Disk 1.Disk 0 is the system disk;Disk 1 is the data disk, which is divided into 3 partitions.A few days ago, when I turned on my comp...
Recruitment of BMS software engineers with generous remuneration. Work location: Huqiu District, Suzhou. Job description: 1. Responsible for software development and debugging of BMS related products....
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
