Complete Three-in-One DDR
Power Solution With BF_CUT
POWER MANAGEMENT
Description
The SC2516 is a fully integrated, Three-in-One DDR Con-
troller supplying power to the VDDQ, VTT and GMCH
rails. A synchronous buck controller provides the high VDDQ
current (20A) at high efficiency, while an internal linear
regulator supplies the termination voltage with 1.8A(min)
Source/Sink capability. Another Synchronous Switcher regu-
lates the 1.5V for GMCH for higher efficiency.
The SC2516 uses the Intel
®
defined Latched BF_Cut
signal to comply with motherboard state transitions. The
regulator uses the 5VDUAL rail to supply VDDQ under all
motherboard states, via the VDDQ switcher. The GMCH
regulator is slaved off the 5V main regulator, using a sepa-
rate UVLO on that rail. Additional logic and supervisory
circuitry complete the functionality of this single chip DDR
power solution in compliance with ACPI requirements.
The MLP package with a copper pad provides excel-
lent thermal impedance while keeping small footprint.
VDDQ short circuit protection along with VTT current limit
as well as two independent thermal shutdown circuits
assure safe operation under all fault conditions.
SC2516
Features
Uses Latched BF_Cut from Intel Glue Chip to control
regulators
High efficiency (90%) VDDQ switcher supplies 20
Amps
External VDDQ divider allows DDRI or DDRII Compat-
ibility
High efficiency GMCH switcher supplies 1.5V from
the 5V rail
Single chip solution complies fully with ACPI power
sequencing specifications
1.8A (min) VTT Source/Sink capability
High current 1Amp gate drives for VDDQ switcher
Independent thermal shutdown for VTT
Fast transient response
Space saving 22-pin MLP package with copper
thermal pad for heatsinking to PC Board
Applications
Power Solution for DDR memory per Intel
motherboard specification
High speed data line termination
Typical Application Circuit
12VCC
SC2516
COMP
FBVDDQ
SS/EN
VTTGND
VTT
VDDQ
AGND
VTTFB
REFSENS
1P5FB
SS_1P5
T H PAD
PGND
BG
TG
BST
5VSBY
COMP_1P5
BF_CUT
TG_1P5
BG_1P5
GND_1P5
POK
5Vdual
1
2
FBVDDQ
3
4
5
VDDQ
6
7
8
VDDQ
9
10
11
22
21
20
19
18
17
16
15
14
13
12
1.5V GMCH
5VCC
5VSBY
FBVDDQ
VDDQ
VTT
Latched BF_CUT
1P5FB
23
1P5FB
ATX_POK
Revision 2, Jun. 2004
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POWER MANAGEMENT
Absolute Maximum Ratings
Parameter
Supply Voltage, BST to AGND
Standby Input Voltage
Inputs
AGND to PGND or LGND
VTT Output Current
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Storage Temperature Range
TG/BG/TG1P5/BG1P5 DC Voltage
TG/BG/TG1P5/BG1P5 AC Voltage
I
O(VTT)
T
A
T
J
θ
JA
θ
JC
T
STG
Symbol
V
BST
V
5VSBY
I/O
SC2516
Complete Three-in-One DDR
Power Solution With BF_CUT
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Maximum
20
7
5VSTBY +0.3, AGND -0.3
0.3
+/ - 2
0 to 70
125
25
4
-65 to 150
BST + 0.3, PGND -0.3
BST + 1.0, PGND -4.0
t < 100 nS
(measured from 50% to 50%)
Units
V
V
V
V
A
o
o
o
o
C
C
C/W
C/W
o
C
V
V
ESD Rating (Human Body Model)
ESD
2
KV
Electrical Characteristics
Unless specified: T
A
= 25
o
C , 5VSBY = 5V
Parameter
5VSBY Voltage
Quiescent Current
BF_CUT Threshold
P_OK Threshold
5VSBY Under Voltage Lockout
VDDQ Feedback Reference
VDDQ Feedback Current
SS/EN Shutdown Threshold
Thermal Shutdown
Thermal Shutdown Hysteresis
Symbol
V
5VSBY
I
Q(5VSBY)
Conditions
Min
4.5
Typ
5
12
8
Max
5.5
16
10
2.4
2.4
3
1.263
Units
V
mA
V
V
V
V
uA
BF_CUT low
BF_CUT High
0.8
0.8
TTL
TTL
2.7
1.25
UVLO
5VSBY
V
REF
I
FB
V
EN(TH)
TJ-SHDN
TJ-HY ST
V
FB
= 1.25V
VDDQ/VTT @ Shutdown
2.4
1.238
-2
0.3
0.5
150
10
V
o
o
C
C
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POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: T
A
= 25
o
C, 5VSBY = 5V.
SC2516
Complete Three-in-One DDR
Power Solution With BF_CUT
Parameter
Switcher
Load Regulation
Oscillator Frequency
Soft Start Current
Maximum Duty Cycle
Overcurrent Trip Voltage
Top Gate Rise Time
Top Gate Fall Time
Bottom Gate Rise Time
Bottom Gate Fall Time
Dead Time
Error Amplifier Transconductance
Error Amplifier Gain @ DC
Error Amplifier Bandwidth
Error Amplifier Source Current
Error Amplifier Sink Current
Internal Ramp
VT T LDO
Output Voltage
Source and Sink Currents
Load Regulation
Error Amplifier Gain
Current Limit
Symbol
Conditions
Min
Typ
Max
Units
I
VDDQ
= 0A to 10A
f
OSC
I
SS
V
SS
= 800mV
225
20
0.2
250
25
75
275
30
80
80
%
KHz
uA
%
%
nS
nS
nS
nS
80
1.2
nS
mS
dB
MHz
85
110
uA
uA
V
V
TRIP
TG
R
TG
F
BG
R
BG
F
t
d
G
m
A
EA
G
BW
% of VDDQ Setpoint
Gate capacitance = 4000pF
Gate capacitance = 4000pF
Gate capacitance = 4000pF
Gate capacitance = 4000pF
70
75
25
25
35
35
20
0.8
R
COMP
= open
50
1
38
5
FB = 0 , COMP = 1V
FB = 1.5V , COMP = 1V
V
RAMP
Peak - to - Peak
55
70
70
90
0.55
VTT
I
VTT
∆
VTT/
∆I
A
EA_VTT
VTT
ILIM
V
VDDQ
= 2.500V
1.235
-1.8
1.250
1.265
+1.8
+1
V
A
%
dB
A
I
VTT
=+1.8A to -1.8A
-1
75
BF_CUT = low
3
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POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: T
A
= 25
o
C,5VSBY = 5V.
SC2516
Complete Three-in-One DDR
Power Solution With BF_CUT
Parameter
1.5V GMCH Switcher
GMCH Feedback Reference
GMCH Feedback current
Load Regulation
Oscillator Frequency
Soft start current
Maximum Duty Cycle
Top Gate Rise Time
Top Gate Fall Time
Bottom Gate Rise Time
Bottom Gate Fall Time
Dead Time
Error Amplifier Transconductance
Error Amplifier Gain @ DC
Error Amplifier Bandwidth
Error Amplifier Sink/Source Current
Internal Ramp
Symbol
Conditions
Min
Typ
Max
Units
V
REF_GMCH
I
FB_GMCH
V
1P5_FB
= 1.25V
I
GMCH
= 0A to 5A
f
OSC
I
SS_1P5
V
SS
= 200mV
1.238
-2
1.25
1.263
V
uA
0.2
225
8
250
10
75
275
12
80
%
KHz
uA
%
nS
nS
nS
nS
120
1.2
nS
mS
dB
MHz
90
uA
V
TG
R
TG
F
BG
R
BG
F
t
d
G
m
A
EA
G
BW
Gate capacitance = 2000pF
Gate capacitance = 2000pF
Gate capacitance = 2000pF
Gate capacitance = 2000pF
50
0.8
40
40
40
40
85
1
38
1
V
1P5_FB
= 0 - 1.5V, COMP = 1V
V
RAMP
Peak - to - Peak
60
75
0.55
Pin Configuration
Ordering Information
Part Numbers
SC2516IMLTR
(1)
SC2516IMLTRT
(1),(2)
Package
MLP-22
MLP-22
Notes:
(1) Only available in tape and reel packaging.
A reel contains 3000 devices.
(2) Lead free and RoHS compliant product.
Note: Pin 23 is the thermal Pad on the bottom of
the device
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POWER MANAGEMENT
Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin Name
COMP
FBVDDQ
SS/EN
VTTGND
VTT
VDDQ
AGND
VTTFB
REFSNS
1P5FB
SS_1P5
POK
GND_1P5
BG_1P5
TG_1P5
BF_CUT
SC2516
Complete Three-in-One DDR
Power Solution With BF_CUT
Pin Function
Compensation pin for the PWM transconductance amplifier for the VDDQ Switcher.
Feedback for the VDDQ regulator. Connect to the VDDQ sense at the point of load.
Soft start capacitor to GND. Pull low to disable controller.
VTT return. Connect to copper plane carrying VTT return current. The trace connecting to this pin
must be able to carry 2 Amps.
VTT Regulator output. Regulates to 1/2 VDDQ. Sources or sinks 1.8 Amps. The trace connecting
to this pin must be able to carry 2 Amps.
VDDQ power input to VTT LDO. The trace connecting to this pin must be able to carry 2 Amps.
Analog ground. Compensation components and the Soft Start Capacitor connect to this ground.
Sense input for the VTT regulator. Connect to Point of Load for the VTT rail.
Sense input for the VDDQ rail. VTT will be regulated to 1/2 t of his voltage. Connect to Point of
Load, where the VREF for the memory is generated.
Sense input for the 1.5V GMCH. Connect to Point of Load for the GMCH rail.
Soft start for 1.5V GMCH switcher . Connect a capacitor to GND.
Connect to power OK signal from ATX power.
Gate Drive return Ground for the 1.5V GMCH regulator. Connect to Source of bottom FET.
Bottom FET Gate drive for the GMCH regulator.
Top FET Gate drive for the GMCH regulator.
Latched BF_CUT input from Glue Chip.
COMP_1P5 Compensation pin for the PWM transconductance amplifier for the1.5V GMCH Switcher
5VSBY
BST
Connect to 5VSTBY input.
The Top and Bottom Gate drive bus.Generated using bootstrap diode/capacitor. An additional
diode is also required to trap the peak Bootstrap voltage for the BG drive. (see typical
application circuit)
Top FET gate drive.
Bottom FET gate drive.
Gate drive return. Keep this pin close to bottom FET source.
20
21
22
TG
BG
PGND
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