• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Retransmit function
• Standard or FWFT mode user selectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT
Input
Register
Output
Register
1K/4K/16K
x36
Dual Ported
Memory
Bus Matching
Port A
Control
Logic
Mail1
Register
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port B
Control
Logic
MRS1
MRS2
PRS
FIFO,
Mail1
Mail2
Reset
Logic
Write
Pointer
Read
Pointer
FF/IR
AF
Status
Flag Logic
36
EF/OR
AE
SPM
FS0/SD
FS1/SEN
A
0–35
B
0–35
BE/FWFT
36
Programmable
Flag Offset
Registers
Timing
Mode
Mail2
Register
MBF2
Cypress Semiconductor Corporation
Document #: 38-06021 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 26, 2002
CY7C43643
CY7C43663
CY7C43683
Pin Configuration
V
CC
AF
NC
MBF2
MBA
MRS1
FS0/SD
GND
GND
FS1/SEN
MRS2
MBB
CSA
FF/IR
NC
PRS
EF/OR
NC
GND
CSB
W/RB
ENB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
MBF1
V
CC
AE
NC
W/RA
ENA
CLKA
GND
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
BE/FWFT
GND
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
GND
A
11
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
TQFP
Top View
CY7C43643
CY7C43663
CY7C43683
CLKB
V
CC
V
CC
B
35
B
34
B
33
B
32
GND
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT
B
25
B
24
BM
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
SIZE
V
CC
B
15
B
14
B
13
B
12
GND
B
11
B
10
GND
A
5
A
4
A
3
SPM
V
CC
A
2
A
1
A
0
GND
B
0
B
1
A
9
A
8
A
7
A
6
B
2
B
3
B
4
B
5
Selection Guide
CY7C43643/63/83
–7
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply
Current (I
CC1
)
Commercial
Industrial
CY7C43643
1K x 36
128 TQFP
CY7C43663
4K x 36
128 TQFP
133
6
7.5
3
0
6
100
CY7C43643/63/83
–10
100
8
10
4
0
8
100
CY7C43643/63/83
–15
66.7
10
15
5
0
8
100
100
CY7C43683
16K x 36
128 TQFP
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
Document #: 38-06021 Rev. *B
GND
B
6
V
CC
B
7
B
8
B
9
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Page 2 of 29
CY7C43643
CY7C43663
CY7C43683
Pin Definitions
Signal Name
A
0–35
AE
Description
Port A Data
Almost Empty
Flag (Port B)
Almost Full Flag
I/O
I
O
Function
36-bit unidirectional data port for side A.
Programmable Almost Empty flag synchronized to CLKA.
It is LOW when the
number of words in the FIFO2 is less than or equal to the value in the Almost Empty A
offset register, X.
[1]
Programmable Almost Full flag synchronized to CLKA.
It is LOW when the number
of empty locations in the FIFO is less than or equal to the value in the Almost Full A
offset register, Y.
[1]
36-bit unidirectional data port for side B.
This is a dual-purpose pin.
During Master Reset, a HIGH on BE will select Big Endian
operation. In this case, depending on the bus size, the most significant byte or word on
Port A is transferred to Port B first. A LOW on BE will select Little Endian operation. In
this case, the least significant byte or word on Port A is transferred to Port B first. After
Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard
Mode, a LOW selects First-Word Fall-Through Mode. Once the timing mode has been
selected, the level on FWFT must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B,
depending on
the state of SIZE. A LOW selects long-word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The level of BM must be static
throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A
and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B
and can be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA
to read or write on
Port A. The A
0–35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB
to read or write on
Port B. The B
0–35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin.
In the CY Standard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A
0–35
outputs, available for
reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
[2]
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA
to read or write
data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB
to read or write
data on Port B.
This is a dual-function pin.
In the CY Standard Mode, the FF function is selected. FF
indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is
selected. IR indicates whether or not there is space available for writing to the FIFO
memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA.
AF
O
B
0–35
BE/FWFT
Port B Data
Big
Endian/First-Wor
d Fall-Through
Select
O
I
BM
Bus Match
Select (Port B)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
CSB
EF/OR
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Port B Full/Input
Ready Flag
I
I
O
ENA
ENB
FF/IR
I
I
O
Notes:
1. When reading from the FIFO under FWFT, ORA/ORB signal should be included in the read logic to ensure proper operation. To read without gating the boundary
flag (e.g., in bursts), use CY standard mode.
2. When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to three clock cycles for flag assertion and deassertion. Refer to
“Designing with CY7C436xx Synchronous FIFO” application notes for more details on flag uncertainties.
Document #: 38-06021 Rev. *B
Page 3 of 29
CY7C43643
CY7C43663
CY7C43683
Pin Definitions
(continued)
Signal Name
FS1/SEN
Description
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
I/O
I
Function
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming.
During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit writes required to program the offset registers
is 20 for the CY7C43643, 24 for the CY7C43663, and 28 for the CY7C43683. The first
bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A
read or write operation.
A HIGH level on MBB chooses a mailbox register
for a Port B read or write operation.
When a read operation is performed on Port B, a HIGH level on MBB selects data from
the Mail1 register for output and a LOW level selects FIFO output register data for output.
Data can only be written into Mail 2 register through Port B (MBB HIGH) and not into
the FIFO memory.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA
that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB
that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO read and write pointers
to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets. It also configures Port B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1 is LOW.
A LOW on this pin initializes the Mail2 register.
A LOW on this pin initializes the FIFO read and write pointers
to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
A LOW strobe on this pin will retransmit data on the FIFO.
This is achieved by
bringing the read pointer back to location zero. The user will still need to perform read
operation to retransmit the data. Retransmit function applies to CY standard mode only.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B.
A LOW
on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must be
static throughout device operation.
A LOW on this pin selects serial programming of partial flag offsets.
A HIGH on
this pin selects parallel programming or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A
for a LOW-to-HIGH transition of CLKA. The A
0–35
outputs are in the high-impedance
state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B
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