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SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset
March 2001
Revised January 2005
SSTV16859
Dual Output 13-Bit Register with
SSTL-2 Compatible I/O and Reset
General Description
The SSTV16859 is a dual output 13-bit register designed
for use with 184 and 232 pin DDR-1 memory modules. The
device has a differential input clock, SSTL-2 compatible
data inputs and a LVCMOS compatible RESET input. The
device has been designed to meet the JEDEC DDR mod-
ule register specifications.
The device has been fabricated on an advanced sub-
micron CMOS process and is designed to operate at power
supplies of less than 3.6V’s.
Features
s
Compliant with DDR-I registered module specifications
s
Operates at 2.5V
±
0.2V V
DD
s
SSTL-2 compatible input structure
s
SSTL-2 compliant output structure
s
Differential SSTL-2 compatible clock inputs
s
Low power mode when device is reset
s
Industry standard 64 pin TSSOP package
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
SSTV16859G
(Note 1)(Note 2)
SSTV16859MTD
(Note 2)
Package Number
BGA96A
MTD64
Package Description
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS500414
www.fairchildsemi.com
SSTV16859
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Name
Q
1A
-Q
13A
Q
1B
-Q
13B
D
1
-D
13
RESET
CK
CK
V
REF
V
DDQ
V
DD
NC
SSTL-2 Compatible Register Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
Negative Master Clock Input
Voltage Reference Pin for SSTL level inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Electrically Isolated No Connect
Description
SSTL-2 Compatible Register Outputs
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Pin Assignment for FBGA
P
R
T
NC
Q
12A
Q
10A
Q
8A
Q
6A
Q
4A
Q
2A
Q
1A
Q
12B
Q
10B
Q
8B
Q
6B
Q
4B
Q
2B
NC
NC
2
NC
Q
13A
Q
11A
Q
9A
Q
7A
Q
5A
Q
3A
Q
13B
Q
11B
Q
9B
Q
7B
Q
5B
Q
3B
Q
1B
NC
NC
3
NC
GND
GND
V
DDQ
V
DDQ
V
DDQ
GND
GND
GND
V
DDQ
V
DDQ
V
DDQ
GND
GND
NC
NC
4
NC
GND
GND
V
DDQ
V
DD
V
DD
GND
GND
V
REF
V
DD
V
DD
V
DDQ
GND
GND
NC
NC
5
NC
NC
NC
D
13
D
11
D
9
D
7
NC
NC
NC
D
5
D
3
D
1
NC
NC
NC
6
NC
NC
NC
D
12
D
10
D
8
RESET
CK
CK
NC
D
6
D
4
D
2
NC
NC
NC
Truth Table
RESET
L
H
H
H
H
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
CK
X or
Floating
Q
n
L
L
H
Q
n-1
Q
n-1
↑
↑
L
H
↓
↓
H
L
L
=
Logic LOW
H
=
Logic HIGH
X
=
Don’t Care but not floating unless noted
↑ =
LOW-to-HIGH Clock Transition
↓ =
HIGH-to-LOW Clock Transition
Q
n-1
= Output Remains in Previously Clocked State
(Top Thru View)
www.fairchildsemi.com
2
SSTV16859
Functional Description
The SSTV16859 is a 13-bit dual register with SSTL-2 com-
patible inputs and outputs. Input data is transferred to out-
put data on the rising edge of the differential clock pair.
When the RESET signal is asserted LOW all outputs are
placed into the LOW logic state and all input comparators
are disabled for power savings. Output glitches are pre-
vented by disabling the internal registers more quickly than
the input comparators. When RESET is removed, the sys-
tem designer must insure the clock and data inputs to the
device are stable during the rising transition of the RESET
signal.
The SSTL-2 data inputs transition based on the value of
V
REF
. V
REF
is a stable system reference used for setting
the trip point of the input buffers of the SSTV16859 and
other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the V
REF
signal.
Logic Diagram
For n
=
1 to 13
3
www.fairchildsemi.com
SSTV16859
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
DDQ
)
Supply Voltage (V
DD
)
Reference Voltage (V
REF
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs Active (Note 4)
DC Input Diode Current (I
IK
)
V
I
<
0V
V
I
>
V
DD
DC Output Diode Current (I
OK
)
V
O
<
0V
V
O
>
V
DDQ
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
DD
or Ground Current
per Supply Pin (I
DD
or Ground)
Storage Temperature Range (T
stg
)
ESD (Human Body Model)
−
0.5V to
+
3.6V
−
0.5V to
+
3.6V
−
0.5V to
+
3.6V
−
0.5V to V
DD
+
0.5V
−
0.5V to V
DDQ
+
0.5V
−
50 mA
+
50 mA
−
50 mA
+
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
≥
7000V
Recommended Operating
Conditions
(Note 5)
Power Supply (V
DDQ
)
Power Supply (V
DD
)
Operating Range
Reference Supply
(V
REF
=
V
DDQ
/2)
Termination Voltage (V
TT
)
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output Current I
OH
/I
OL
V
DD
=
2.3V to 2.7V
Free Air Operating Temperature (T
A
)
0V to V
DDQ
1.15 to 1.35
V
REF
±
40 mV
0 to V
DD
V
DDQ
to 2.7V
2.3V to 2.7V
±
20 mA
0
°
C to
+
70
°
C
Note 3:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 4:
IO Absolute Maximum Rating must be observed.
Note 5:
The RESET input of the device must be held at V
DD
or GND to
ensure proper device operation. The differential inputs must not be floating,
unless RESET is asserted LOW.
DC Electrical Characteristics
(2.3V
≤
V
DD
≤
2.7V)
Symbol
V
IKL
V
IKH
V
IH-AC
V
IL-AC
V
IH-DC
V
IL-DC
V
IH
V
IL
V
ICR
V
I(PP)
V
OH
V
OL
I
I
I
DD
Parameter
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Conditions
I
I
= −18
mA
I
I
= +18
mA
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
0.97
360
2.3 to 2.7
2.3
2.3 to 2.7
2.3
2.7
V
DD
−
0.2
1.95
0.2
0.35
±5.0
10
2.7
25
mA
1.7
0.7
1.53
V
REF
+150mV
V
REF
−150mV
V
DD
(V)
2.3
2.3
V
REF
+310mV
V
REF
−310mV
Min
Typ
Max
−1.2
3.5
Units
V
V
V
V
V
V
V
V
V
mV
V
V
µA
µA
Common Mode Input Voltage Range CK, CK
Peak to Peak Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
Static Standby
Static Operating
CK, CK
I
OH
= −100 µA
I
OH
= −16
mA
I
OL
=
100
µA
I
OL
=
16 mA
V
I
=
V
DD
or GND
RESET
=
GND, I
O
=
0
RESET
=
V
DD
, I
O
=
0
V
I
=
V
IH(AC)
or V
IL(AC)
RESET
=
V
DD
, I
O
=
0
V
I
=
V
IH(AC)
or V
IL(AC)
CK, CK Duty Cycle 50%
Dynamic Operating Current
per Data Input
RESET
=
V
DD
, I
O
=
0
V
I
=
V
IH(AC)
or V
IL(AC)
CK, CK Duty Cycle 50%
Data Input
=
½ Clock
Rate 50% Duty Cycle
2.7
I
DDD
Dynamic Operating Current
Clock Only
120
µA/MHz
15
µA/MHz
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4
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