HM52Y64165F Series
HM52Y64805F Series
HM52Y64405F Series
64M SDRAM
133 MHz/125 MHz
1-Mword
×
16-bit
×
4-bank/2-Mword
×
8-bit
×
4-bank
/4-Mword
×
4-bit
×
4-bank
ADE-203-974 (Z)
Preliminary
Rev. 0.0
Oct. 30, 1998
Description
The Hitachi HM52Y64165F is a 64-Mbit SDRAM organized as 1048576-word
×
16-bit
×
4 bank. The Hita-
chi HM52Y64805F is a 64-Mbit SDRAM organized as 2097152-word
×
8-bit
×
4 bank. The Hitachi
HM52Y64405F is a 64-Mbit SDRAM organized as 4194304-word
×
4-bit
×
4 bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
•
•
•
•
•
•
•
2.5 V power supply
Clock frequency: 133 MHz/125 MHz (max)
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
— Sequential (BL = 1/2/4/8/full page)
— Interleave (BL = 1/2/4/8)
Programmable CAS latency: 2/3
Byte control by DQM:DQM (HM52Y64805F/HM52Y64405F)
: DQMU/DQML (HM52Y64165F)
Refresh cycles: 4096 refresh cycles/64 ms
2 variations of refresh
— Auto refresh
— Self refresh
Full page burst length capability
— Sequential burst
•
•
•
•
•
HM52Y64165F Series HM52Y64805F Series HM52Y64405F Series
— Burst stop capability
Ordering Information
Type No.
HM52Y64165FTT-75
HM52Y64165FTT-80
HM52Y64805FTT-75
HM52Y64805FTT-80
HM52Y64405FTT-75
HM52Y64405FTT-80
Frequency
133 MHz
125 MHz
133 MHz
125 MHz
133 MHz
125 MHz
Package
400-mil 54-pin plastic TSOP II (TTP-54D)
Pin Arrangement (HM52Y64165F)
54-pin TSOP
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ15 Data-input/output
2
A0 to A11
A0 to A7
Pin name
WE
CLK
CKE
V
CC
Function
Write enable
Clock input
Clock enable
Power for internal circuit
DQMU/DQML Input/output mask
Bank select address A12/A13 (BS)
HM52Y64165F Series HM52Y64805F Series HM52Y64405F Series
Pin name
CS
RAS
CAS
Function
Chip select
Row address strobe command
Column address strobe command
Pin name
V
SS
V
CC
Q
V
SS
Q
NC
Function
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Pin Arrangement (HM52Y64805F)
54-pin TSOP
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ7
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
A0 to A11
A0 to A8
Pin name
WE
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write enable
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Bank select address A12/A13 (BS)
3
HM52Y64165F Series HM52Y64805F Series HM52Y64405F Series
Pin Arrangement (HM52Y64405F)
54-pin TSOP
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
A13
A12
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
NC
V
SS
Q
NC
DQ2
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A13
Function
Address input
Row address
Column address
DQ0 to DQ3
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
A0 to A11
A0 to A9
Pin name
WE
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write enable
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Bank select address A12/A13 (BS)
4
HM52Y64165F Series HM52Y64805F Series HM52Y64405F Series
Block Diagram (HM52Y64165F)
A0 to A13
A0 to A7
A0 to A13
Column address
counter
Column address
buffer
Row address
buffer
Refresh
counter
Row decoder
Row decoder
Row decoder
Row decoder
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array
Column decoder
Memory array
Column decoder
Memory array
Column decoder
Sense amplifier & I/O bus
Memory array
Column decoder
Bank 0
Bank 1
Bank 2
Bank 3
4096 row
X 256 column
X 16 bit
4096 row
X 256 column
X 16 bit
4096 row
X 256 column
X 16 bit
4096 row
X 256 column
X 16 bit
Input
buffer
Output
buffer
Control logic &
timing generator
DQ0 to DQ15
RAS
CAS
DQMU
/DQML
CLK
CKE
WE
CS
5
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