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IS43LR32160B-75BLI

Description
DDR DRAM, 16MX32, 6ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90
Categorystorage    storage   
File Size2MB,42 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Environmental Compliance  
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IS43LR32160B-75BLI Overview

DDR DRAM, 16MX32, 6ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90

IS43LR32160B-75BLI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeDSBGA
package instructionTFBGA, BGA90,9X15,32
Contacts90
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
interleaved burst length2,4,8,16
JESD-30 codeR-PBGA-B90
JESD-609 codee1
length13 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width32
Humidity sensitivity level3
Number of functions1
Number of ports1
Number of terminals90
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16MX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA90,9X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)260
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length2,4,8,16
Maximum standby current0.00001 A
Maximum slew rate0.11 mA
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature40
width8 mm
IS43LR32160B, IS46LR32160B
Advanced Information
4M
x
32Bits
x
4Banks Mobile DDR SDRAM
Description
The IS43/46LR32160B is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4,194,304 words x
32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted
on a 32-bit bus. The double data rate architecture is essentially a 2
N
prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are
compatible with LVCMOS.
Features
• JEDEC standard 1.8V power supply.
• VDD = 1.8V, VDDQ = 1.8V
• Four internal banks for concurrent operation
• MRS cycle with address key programs
- CAS latency 2, 3 (clock)
- Burst length (2, 4, 8, 16)
- Burst type (sequential & interleave)
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising
edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• 64ms refresh period (8K cycle)
• Auto & self refresh
• Concurrent Auto Precharge
• Maximum clock frequency up to 166MHZ
• Maximum data rate up to 333Mbps/pin
• Special Power Saving supports.
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self Refresh)
- Deep Power Down Mode
- Programmable Driver Strength Control by Full Strength
or 1/2, 1/4, 1/8 of Full Strength
• LVCMOS compatible inputs/outputs
• 90-Ball FBGA package
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev.00B | Dec. 2010
www.issi.com
- dram@issi.com
1

IS43LR32160B-75BLI Related Products

IS43LR32160B-75BLI IS46LR32160B-75BLA1 IS43LR32160B-75BL IS43LR32160B-75BLI-TR IS46LR32160B-75BLA2 IS46LR32160B-75BLA2-TR
Description DDR DRAM, 16MX32, 6ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90 16MX32 DDR DRAM, 6ns, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90 DDR DRAM, 16MX32, 6ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90 DDR DRAM, 16MX32, 6ns, CMOS, PBGA90 16MX32 DDR DRAM, 6ns, PBGA90, 8 X 13 MM, LEAD FREE, MO-207, FBGA-90 DDR DRAM, 16MX32, 6ns, CMOS, PBGA90
Is it Rohs certified? conform to conform to conform to conform to conform to conform to
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Reach Compliance Code compliant compliant compliant compliant compliant compliant
Maximum access time 6 ns 6 ns 6 ns 6 ns 6 ns 6 ns
Maximum clock frequency (fCLK) 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
I/O type COMMON COMMON COMMON COMMON COMMON COMMON
interleaved burst length 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16
JESD-30 code R-PBGA-B90 R-PBGA-B90 R-PBGA-B90 R-PBGA-B90 R-PBGA-B90 R-PBGA-B90
memory density 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit 536870912 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM DDR DRAM
memory width 32 32 32 32 32 32
Number of terminals 90 90 90 90 90 90
word count 16777216 words 16777216 words 16777216 words 16777216 words 16777216 words 16777216 words
character code 16000000 16000000 16000000 16000000 16000000 16000000
Maximum operating temperature 85 °C 85 °C 70 °C 85 °C 105 °C 105 °C
Minimum operating temperature -40 °C -40 °C - -40 °C -40 °C -40 °C
organize 16MX32 16MX32 16MX32 16MX32 16MX32 16MX32
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA TFBGA FBGA TFBGA FBGA
Encapsulate equivalent code BGA90,9X15,32 BGA90,9X15,32 BGA90,9X15,32 BGA90,9X15,32 BGA90,9X15,32 BGA90,9X15,32
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, FINE PITCH
power supply 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192 8192 8192 8192
Continuous burst length 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16 2,4,8,16
Maximum standby current 0.00001 A 0.00001 A 0.00001 A 0.00001 A 0.00001 A 0.00001 A
Maximum slew rate 0.11 mA 0.11 mA 0.11 mA 0.11 mA 0.11 mA 0.11 mA
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V
surface mount YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form BALL BALL BALL BALL BALL BALL
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Is it lead-free? Lead free Lead free Lead free - Lead free -
Parts packaging code DSBGA DSBGA DSBGA - DSBGA -
package instruction TFBGA, BGA90,9X15,32 TFBGA, BGA90,9X15,32 TFBGA, BGA90,9X15,32 - TFBGA, BGA90,9X15,32 -
Contacts 90 90 90 - 90 -
ECCN code EAR99 EAR99 EAR99 - EAR99 -
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST - FOUR BANK PAGE BURST -
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH - AUTO/SELF REFRESH -
JESD-609 code e1 e1 e1 - e1 -
length 13 mm 13 mm 13 mm - 13 mm -
Humidity sensitivity level 3 3 3 - 3 -
Number of functions 1 1 1 - 1 -
Number of ports 1 1 1 - 1 -
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS - SYNCHRONOUS -
Peak Reflow Temperature (Celsius) 260 260 260 - 260 -
Maximum seat height 1.2 mm 1.2 mm 1.2 mm - 1.2 mm -
self refresh YES YES YES - YES -
Maximum supply voltage (Vsup) 1.95 V 1.95 V 1.95 V - 1.95 V -
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V - 1.7 V -
Terminal surface Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) Tin/Silver/Copper (Sn/Ag/Cu) - Tin/Silver/Copper (Sn/Ag/Cu) -
Maximum time at peak reflow temperature 40 40 40 - 40 -
width 8 mm 8 mm 8 mm - 8 mm -

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