Features
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Supply Voltage up to 40V
R
DSon
Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C
Up to 1.0A Output Current
Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
Capable of Switching Loads such as DC Motors, Bulbs, Resistors, Capacitors, and
Inductors
PWM Capability up to 25 kHz for Each High-side Output Controlled by External PWM
Signal
No Shoot-through Current
Very Low Quiescent Current I
VS
< 5 µA in Standby Mode over Total Temperature Range
Outputs Short-circuit Protected
Selective Overtemperature Protection for Each Switch and Overtemperature
Prewarning
Undervoltage Protection
Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
QFN18 Package
Triple
Half-bridge
Driver with SPI
and PWM
ATA6831
1. Description
The ATA6831 provides fully protected driver interfaces designed in SOI technology.
They are used to allow a microcontroller to control up to 3 different loads in automo-
tive and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to
1.0A. Due to the enhanced PWM signal (up to 25 kHz) it is possible to generate a
smooth control of, for example, a DC motor without any noise. The drivers are inter-
nally connected to form 3 half-bridges and can be controlled separately from a
standard serial data interface, enabling all kinds of loads, such as bulbs, resistors,
capacitors and inductors, to be combined. The IC design especially supports the
application of H-bridges to drive DC motors.
Protection is guaranteed with respect to short-circuit conditions, overtemperature and
undervoltage. Various diagnostic functions and a very low quiescent current in
standby mode enable a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
4908G–AUTO–07/10
Figure 1-1.
Block Diagram
S
I
O
S
C
O
L
D
P
H
3
P
L
3
P
H
2
P
L
2
P
H
1
P
L
1
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
10
VS1
11
Input register
Ouput register
Serial interface
Charge
pump
L
S
1
T
P
VS2
DI
4
P
S
F
I
N
H
O
V
L
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
n. H
u. S
3
L
S
3
H
S
2
L
S
2
H
S
1
CLK
5
CS
3
DO
7
PWM
6
Control
logic
Power on
reset
8
GND
14
Fault
detector
Fault
detector
Fault
detector
Fault
detector
Fault
detector
Fault
detector
UV
protection
9
VCC
GND
Thermal
protection
17
GND
18
1
OUT3S
2
OUT3F
13
OUT2S
12
OUT2F
16
OUT1S
15
OUT1F
GND
2
ATA6831
4908G–AUTO–07/10
ATA6831
2. Pin Configuration
Figure 2-1.
Pinning QFN18
PGND3
PGND1
OUT1S
OUT1F
PGND2
OUT2S
OUT3S
OUT3F
CS
DI
CLK
PWM
1
2
3
4
5
6
18 17 16 15 14 13
12
11
10
9
8
7
OUT2F
VS2
VS1
VCC
GND
DO
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Description
Symbol
OUT3S
OUT3F
CS
DI
CLK
PWM
DO
GND
VCC
VS1
VS2
OUT2F
OUT2S
PGND2
OUT1F
OUT1S
PGND1
PGND3
Function
Used only for final testing, to be connected to OUT3F
Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
Chip select input; 5V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control
device; DI expects a 16-bit control word with LSB transferred first
Serial clock input; 5V CMOS logic level input with internal pull-down;
controls serial data input interface and internal shift register (f
max
= 2 MHz)
PWM input; 5V CMOS logic level input with internal pull-down
Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is
selected by CS = low; this allows several ICs to operate on only one data-output line
Ground
Logic supply voltage (5V)
Power supply for output stages OUT1 and OUT2; internal supply
Power supply for output stages OUT2 and OUT3; internal supply
Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
Used only for final testing, to be connected to OUT2F
Power ground OUT2
Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
Used only for final testing, to be connected to OUT1F
Power ground OUT1
Power ground OUT3
3
4908G–AUTO–07/10
3. Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be
transferred first. Execution of new input data is enabled on the rising edge of the CS signal.
When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next
rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
CS
Data Transfer
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
PL1
7
PH1
8
PL2
9
PH2
10
PL3
11
PH3
12
OLD
13
OCS
14
15
SI
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVl
INH
PSF
Table 3-1.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Data Protocol
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
PL1
PH1
PL2
PH2
PL3
PH3
OLD
OCS
SI
Function
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Output LS1 additionally controlled by PWM Input
Output HS1 additionally controlled by PWM Input
See PL1
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by the standby function because the digital
part is still powered)
4
ATA6831
4908G–AUTO–07/10
ATA6831
Table 3-2.
Bit
0
Output Data Protocol
Output (Status)
Register
TP
Function
Temperature prewarning: high = warning
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Over-load detected: set high, when at least one output is switched off
by a short-circuit condition or an overtemperature event. Bits 1 to 6 can
be used to detect the affected switch
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
Power-supply fail: undervoltage at pin VS detected
1
Status LS1
2
Status HS1
3
4
5
6
7
8
9
10
11
12
13
Status LS2
Status HS2
Status LS3
Status HS3
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVL
14
15
INH
PSF
After power-on reset, the input register has the following status:
Bit 15 Bit 14
SI
OCS
H
H
Bit 13
OLD
H
Bit 12
PH3
L
Bit 11
PL3
L
Bit 10
PH2
L
Bit 9
PL2
L
Bit 8
PH1
L
Bit 7
PL1
L
Bit 6
HS3
L
Bit 5
LS3
L
Bit 4
HS2
L
Bit 3
LS2
L
Bit 2
HS1
L
Bit 1
LS1
L
Bit 0
SRR
L
The following patterns are used to enable internal test modes of the IC. Do not use these pat-
terns during normal operation.
Bit 15 Bit 14
H
H
H
H
H
H
Bit 13
(OCS)
H
H
H
Bit 12
H
L
L
Bit 11
H
L
L
Bit 10
L
H
L
Bit 9
L
H
L
Bit 8
L
L
H
Bit 7
L
L
H
Bit 6
(HS3)
L
L
L
Bit 5
(LS3)
L
L
L
Bit 4
(HS2)
L
L
L
Bit 3
(LS2)
L
L
L
Bit 2 Bit 1
(HS1) (LS1)
L
L
L
L
L
L
Bit 0
(SRR)
L
L
L
5
4908G–AUTO–07/10
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