MACH221-15JC datasheet, PDF - EEWORLD Datasheet

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MACH221-15JC: DescriptionEE PLD, 19ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68; CategoryProgrammable logic devices Programmable logic; File Size827KB，30 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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MACH221-15JC Overview

EE PLD, 19ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68

MACH221-15JC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	unknown
Other features	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency	50 MHz
In-system programmable	NO
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
JTAG BST	NO
length	24.2062 mm
Dedicated input times	4
Number of I/O lines	48
Number of macro cells	96
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	EE PLD
propagation delay	19 ns
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.2062 mm

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MACH221-15JC Related Products

	MACH221-15JC	MACH221-10JC	MACH221-10JI	MACH221-12JC	MACH221-12JI	MACH221-14JI	MACH221-18JI	MACH221-7JC
Description	EE PLD, 19ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 14ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 12ns, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 16ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 17ns, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 19.5ns, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 23ns, CMOS, PQCC68, PLASTIC, LCC-68	EE PLD, 12.5ns, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68
Maker	AMD	AMD	AMD	AMD	AMD	AMD	AMD	AMD
Parts packaging code	LCC	LCC	LCC	LCC	LCC	LCC	LCC	LCC
package instruction	QCCJ, LDCC68,1.0SQ	QCCJ, LDCC68,1.0SQ	QCCJ,	QCCJ, LDCC68,1.0SQ	QCCJ,	QCCJ,	QCCJ,	QCCJ, LDCC68,1.0SQ
Contacts	68	68	68	68	68	68	68	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	BURIED MACROCELLS; 4 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency	50 MHz	80 MHz	80 MHz	66.7 MHz	65 MHz	53 MHz	40 MHz	95 MHz
JESD-30 code	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68	S-PQCC-J68
length	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm
Dedicated input times	4	4	4	4	4	4	4	4
Number of I/O lines	48	48	48	48	48	48	48	48
Number of terminals	68	68	68	68	68	68	68	68
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	85 °C	85 °C	85 °C	70 °C
organize	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O	4 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	19 ns	14 ns	12 ns	16 ns	17 ns	19.5 ns	23 ns	12.5 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm
Maximum supply voltage	5.25 V	5.25 V	5.5 V	5.25 V	5.5 V	5.5 V	5.5 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V	4.5 V	4.75 V	4.5 V	4.5 V	4.5 V	4.75 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal form	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD
width	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm	24.2062 mm
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	-	-	-	incompatible
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	NOT SPECIFIED
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	-	NOT SPECIFIED

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