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LC MOS
Quad 8-Bit D/A Converter
AD7226
FEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages
Microprocessor-Compatible
TTL/CMOS-Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
MSB
DATA
(8-BIT)
LSB
2
FUNCTIONAL BLOCK DIAGRAM
V
REF
V
DD
LATCH A
DAC A
A
V
OUT
A
D
A
T
A
B
U
S
LATCH B
DAC B
B
V
OUT
B
LATCH C
DAC C
C
V
OUT
C
LATCH D
WR
A1
A0
CONTROL
LOGIC
DAC D
D
V
OUT
D
AD7226
V
SS
AGND
AGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7226 contains four 8-bit voltage-output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is
loaded when
WR
goes low. The control logic is speed-compat-
ible with most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from 2 V to 12.5 V with dual supplies. The part is also specified
for single supply operation at a reference of 10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC
2
MOS) process, which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single-Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin package allows a dramatic reduction in board
space requirements and offers increased reliability in systems
using multiple converters. Its pinout is aimed at optimizing
board layout with all the analog inputs and outputs at one
end of the package and all the digital inputs at the other.
REV.
D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax:
781-461-3113
© 20
11
Analog Devices, Inc. All rights reserved.
AD7226–SPECIFICATIONS
DUAL SUPPLY
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale Temperature Coefficient
Zero Code Error
Zero Code Error Temperature Coefficient
REFERENCE INPUT
Voltage Range
Input Resistance
Input Capacitance
3
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
Voltage Output Settling Time
4
Digital Crosstalk
Minimum Load Resistance
POWER SUPPLIES
V
DD
Range
I
DD
I
SS
SWITCHING CHARACTERISTICS
4, 5
Address to Write Setup Time, t
AS
Address to Write Hold Time, t
AH
Data Valid to Write Setup Time, t
DS
Data Valid to Write Hold Time, t
DH
Write Pulsewidth, t
WR
(V
DD
= 11.4 V to 16.5 V, V
SS
= –5 V 10%, AGND = DGND = 0 V; V
REF
= +2 V to (V
DD
– 4 V)
1
,
unless otherwise noted. All Specifications T
MIN
to T
MAX
unless otherwise noted.)
K, B Versions
2
8
±
1
±
0.5
±
1
±
0.5
±
20
±
20
±
50
2 to (V
DD
– 4)
2
50
200
2.4
0.8
±
1
8
Binary
2.5
4
10
2
11.4/16.5
13
11
0
0
50
0
50
Unit
Bits
LSB max
LSB max
LSB max
LSB max
ppm/∞C typ
mV max
mV/∞C
typ
V min to V max
kW min
pF min
pF max
V min
V max
mA
max
pF max
Conditions/Comments
V
DD
= 15 V
±
5%, V
REF
= 10 V
Guaranteed Monotonic
V
DD
= 14 V to 16.5 V, V
REF
= +10 V
Occurs when each DAC is loaded with all 0s.
Occurs when each DAC is loaded with all 1s.
V
IN
= 0 V or V
DD
V/ms min
ms
max
nV secs typ
kW min
V min/V max
mA max
mA max
ns min
ns min
ns min
ns min
ns min
V
REF
= 10 V; Settling Time to
±
1/2 LSB
V
OUT
= 10 V
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
Outputs Unloaded; V
IN
= V
INL
or V
INH
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
5
Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
–2–
REV.
D
AD7226
SINGLE SUPPLY
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error
Differential Nonlinearity
REFERENCE INPUT
Input Resistance
Input Capacitance
3
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current
Input Capacitance
Input Coding
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
4
Voltage Output Settling Time
4
Digital Crosstalk
Minimum Load Resistance
POWER SUPPLIES
V
DD
Range
I
DD
NOTES
1
Maximum possible reference voltage.
2
Temperature ranges are as follows:
K Version: –40∞C to +85∞C
B Version: –40∞C to +85∞C
3
Guaranteed by design. Not production tested.
4
Sample Tested at 25∞C to ensure compliance.
Specifications subject to change without notice.
(V
DD
= 15 V 5%, V
SS
= AGND = DGND = O V; V
REF
= 10 V
1
unless otherwise noted.
All specifications T
MIN
to T
MAX
unless otherwise noted.)
K, B Versions
2
8
±
2
±
1
2
50
200
2.4
0.8
±
1
8
Binary
2
4
10
2
14.25/15.75
13
Unit
Bits
LSB max
LSB max
kW min
pF min
pF max
V min
V max
mA
max
pF max
Conditions/Comments
Guaranteed Monotonic
Occurs when each DAC is loaded with all 0s.
Occurs when each DAC is loaded with all 1s.
V
IN
= 0 V or V
DD
V/ms min
ms
max
nV secs typ
kW min
V min/V max
mA max
Settling Time to
±
1/2 LSB
V
OUT
= +10 V
For Specified Performance
Outputs Unloaded; V
IN
= V
INL
or V
INH
ABSOLUTE MAXIMUM RATINGS
1
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
DD
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V, V
DD
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
OUT
to AGND
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 500 mW
Derates above 75∞C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/∞C
Operating Temperature
Commercial (K Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
Industrial (B Version) . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 50 mA.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV.
D
–3–
AD7226
PIN CONFIGURATIONS
DIP and SOIC/SSOP
V
OUT
B
1
V
OUT
A
2
V
SS 3
V
REF 4
AGND
5
V
OUT
C
V
OUT
D
V
DD
A0
A1
20
19
18
17
AD7226
16
DGND
6
TOP VIEW
15
WR
(Not to Scale)
14
DB0(LSB)
DB7 (MSB)
7
DB6
8
DB5
9
DB4
10
13
12
11
DB1
DB2
DB3
PLCC
V
OUT
B
1
V
OUT
C
20
3
2
V
OUT
D
19
18
V
DD
17
A0
16
A1
15
WR
14
DB0(LSB)
13
V
REF
4
AGND
5
DGND
6
DB7 (MSB)
7
DB8
8
9
10
11
12
V
SS
DB5
TOP VIEW
(Not to Scale)
DB4
V
OUT
A
AD7226
DB3
DB2
TERMINOLOGY
TOTAL UNADJUSTED ERROR
DIFFERENTIAL NONLINEARITY
This is a comprehensive specification that includes full-scale
error, relative accuracy and zero code error. Maximum output
voltage is V
REF
– 1 LSB (ideal), where 1 LSB (ideal) is V
REF
/
256. The LSB size will vary over the V
REF
range. Hence the zero
code error will, relative to the LSB size, increase as V
REF
decreases.
Accordingly, the total unadjusted error, which includes the zero
code error, will also vary in terms of LSB’s over the V
REF
range.
As a result, total unadjusted error is specified for a fixed refer-
ence voltage of 10 V.
RELATIVE ACCURACY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of
±
1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter
due to a change in the digital input code to another of the con-
verters. It is specified in nV secs and is measured at V
REF
= 0 V.
FULL SCALE ERROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
Relative Accuracy or endpoint nonlinearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
allowing for zero and full-scale error and is normally expressed
in LSB’s or as a percentage of full-scale reading.
DB1
–4–
REV.
D
FPGA/CPLD
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