2.5V/3V, 3.0GHz
CML AnyGate™ANY LOGIC
w/50
Ω
or 100
Ω
OUTPUTS
FEATURES
s
Guaranteed AC parameters over temperature:
• f
MAX
> 3.0GHz (SY55851A)
• t
r
/ t
f
< 100ps
• Propagation delay < 280ps
s
Guaranteed operation over –40
°
C to +85
°
C
temperature range
s
Wide supply voltage range: 2.3V to 3.6V
s
Single IC provides 8 logic functions
s
2:1 MUX capability
s
Fully differential I/O
s
Source terminated CML outputs for fast edge rates:
• SY55851 for 100
Ω
load
• SY55851A for 50
Ω
load
s
Guaranteed matched propagation delays:
• Select (S)-to-out: < 280ps
• Input (A and B)-to-out: < 280ps
s
Accepts PECL, LVPECL, CML input signals
s
Functions as a PECL/LVPECL-to-CML translator
s
Available in a 10-pin (3mm
×
3mm) MSOP package
SuperLite™
SY55851
SY55851A
DESCRIPTION
The SY55851 and SY55851A are highly flexible,
universal logic gates capable of up to 3.0GHz operation
(SY55851A). These AnyGate differential logic devices
will produce all possible logic functions of two Boolean
variables. They can be configured as any of the following
gates: AND, NAND, OR, NOR, XOR, XNOR, DELAY,
NEGATION (NOT). The SY55851 and SY55851A can
also function as a 2-input multiplexer.
The SY55851 has an output stage optimized for 100Ω
loads, and the SY55851A is optimized for 50Ω loads.
The differential inputs for both devices are normally
terminated with a single resistor (100Ω) between the true
and complement pins.
APPLICATIONS
s
Port bypass
s
Data communication systems
s
Wireless communication systems
s
Telecom systems
PIN CONFIGURATION
S 1
/S 2
A 3
/A 4
GND 5
MSOP
10 VCC
FUNCTIONAL BLOCK DIAGRAM
S
2
9 /B
8 B
7 Q
6 /Q
B
A
2
0 S
1
2
2
Q
SY55851 and SY55851A
PIN NAMES
Pin
A, /A
B, /B
Q, /Q
S, /S
GND
V
CC
AnyGate and SuperLite are trademarks of Micrel, Inc.
Rev.: A
Amendment: /1
Function
CML, PECL, LVPECL Input
CML, PECL, LVPECL Input
Differential CML Output
CML, PECL, LVPECL Input Selector
Ground
V
CC
1
Issue Date: September 2001
Micrel
SuperLite™
SY55851
SY55851A
PIN DESCRIPTIONS
A, /A – CML Input (Differential)
This is one of the differential inputs to the logic block.
For a 2-variable logic function, it is either a constant
value or a Boolean input. For a 2-input mux, this signal
represents the output when S is set to logic zero.
B, /B – CML Input (Differential)
This is one of the differential inputs to the logic block.
For a 2-variable logic function, it is either a constant
value or a Boolean input. For a 2-input mux, this signal
represents the output when S is set to logic one.
Q, /Q – CML Output (Differential)
This is the differential CML output for the logic block. For
termination guidelines, see
Figure 3.
S, /S – CML Input (Differential)
This differential CML input is one of the inputs to the
logic block. It represents either one Boolean input for a
2-variable logic function, or the select input for a 2-input
mux.
FUNCTIONAL DESCRIPTION
Establishing Static Logic Inputs
The true pin of an input pair is internally biased to ground
through a 75kΩ resistor. The complement pin of an input
pair is internally biased to V
CC
/2 through an internal voltage
divider consisting of two 75kΩ resistors. Since some logic
functions necessitate an output to be connected to two
inputs, SY55851/A inputs have no internal terminations.
Typically, one resistor between the true and complement
input is all that is required, as per
Figure 3.
To keep an
input at static logic zero at V
CC
≥
3.0V, leave both inputs
unconnected or tie the complement input to V
CC
. For V
CC
<
3.0V applications, connect the complement input to V
CC
and leave the true input unconnected. To make an input
static logic one, connect the true input to V
CC
, and leave
the complement input unconnected. These are the only safe
ways to cause inputs to be at a static value. In particular,
no input pin should be directly connected to ground. All NC
(no connect) pins should be unconnected.
V
CC
NC
Input
/Input
NC
NC
Input
/Input
For V
CC
> 3.0V Applications
Figure 1. Hard Wiring A Logic “1”
(1)
NOTE:
1. Input is either A, B, S input, and /Input is either /A, /B, /S input.
NC
VCC
Input
/Input
For V
CC
< 3.0V Applications
Figure 2. Hard Wiring A Logic “0”
(1)
2
Micrel
SuperLite™
SY55851
SY55851A
TRUTH TABLES
β
AND/NAND
A
Q
α⋅β
/Q
(α
⋅ β)
L
L
L
L
α
B
L
H
L
H
β
S
L
L
H
H
α⋅β
Q
L
L
L
H
(α⋅β)
(α⋅
/Q
H
H
H
L
NC
V
CC
α
S
A /S
/A
B
/B
β
S
A /S
/A
B
/B
OR/NOR
Q
α+β
/Q
(α
+ β)
α
A
L
H
L
H
B
H
H
H
H
β
S
L
L
H
H
α
+
β
Q
L
H
H
H
(α
+
β)
/Q
H
L
L
L
α
V
CC
NC
β
S
A /S
/A
B
/B
XOR/XNOR
α
A
Q
α⊕β
/Q
(α
⊕ β)
B
H
H
L
L
β
S
L
H
L
H
α⊕β
Q
L
H
H
L
(α ⊕ β)
/Q
H
L
L
H
α
L
L
H
H
NC
α
V
CC
S
A /S
/A
B
/B
DELAY/NEGATION
Q
α
/Q
α
α
A
L
H
B
X
X
S
L
L
α
Q
L
H
α
/Q
H
L
V
CC
S
A /S
/A
B
/B
NC
Q
β
/Q
β
A
X
X
β
B
L
H
S
H
H
β
Q
L
H
β
/Q
H
L
β
S
2:1 MUX
A
B
0
S
Q
B
A
Q
1
H
L
3
Micrel
SuperLite™
SY55851
SY55851A
CML TERMINATION AND TTL INTERFACE
All inputs accept the output from any other member of
this family. All outputs are source terminated 100Ω or 50Ω
CML differential drivers as shown in Figure 3. All inputs to
the SY55851/A must be externally terminated. SY55851/A
inputs are designed to accept a termination resistor between
the true and complement inputs of a differential pair. 0402
form factor chip resistors will fit with some trace fanout.
V
CC
V
CC
100Ω
100Ω
Q
/Q
100Ω
200Ω
100Ω
50Ω
50Ω
Q
/Q
50Ω
100Ω
50Ω
8mA
16mA
SY55851
SY55851A
Figure 3a. SY55851
100
Ω
Load CML Output
Figure 3b. Differentially Terminated SY55851A
(50
Ω
Load CML Output)
V
CC
V
CC
100Ω
100Ω
Q
/Q
100Ω
100Ω
50Ω
100Ω
50Ω
1k
549‰
S
/S
1.47k
TTL
Driver
1k
SY55851
SY55851A
V
CC
V
CC
V
CC
V
CC ‡
V
CC
(TTL Driver)
8mA
SY55851
Figure 3c. Differentially Terminated SY55851
(50
Ω
Load CML Output)
Figure 4. Interfacing TTL-to-CML Select Inputs
4
Micrel
SuperLite™
SY55851
SY55851A
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CC
V
IN
V
OUT
T
A
T
store
θ
JA
θ
JC
Power Supply Voltage
Input Voltage
CML Output Voltage
Operating Temperature Range
Storage Temperature Range
Package Thermal Resistance
(Junction-to-Ambient)
Package Thermal Resistance
(Junction-to-Case)
–Still-Air (multi-layer PCB)
–500lfpm (multi-layer PCB)
Rating
Value
–0.5 to +6.0
–0.5 to V
CC
+0.5
V
CC
–1.0 to V
CC
+0.5
–40 to +85
–65 to +150
113
96
42
Unit
V
V
V
°C
°C
°C/W
°C/W
°C/W
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended
periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
T
A
= –40°C to +85°C
(1)
Symbol
V
CC
I
CC
Parameter
Power Supply Voltage
Power Supply Current
SY55851
SY55851A
Min.
2.3
—
—
Typ.
—
—
46
Max.
3.6
40
60
Unit
V
mA
mA
No Load
No Load
Condition
CML DC ELECTRICAL CHARACTERISTICS
V
CC
= 2.3V to 3.6V; GND = 0V; T
A
= –40°C to +85°C
(1)
Symbol
V
ID
V
IH
V
IL
V
OH
V
OL
V
OUT
Parameter
Differential Input Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
(2)
SY55851
SY55851A
R
OUT
Output Source Impedance
SY55851
SY55851A
Min.
100
1.6
1.5
V
CC
– 0.040
V
CC
– 1.00
0.650
—
—
—
80
40
Typ.
—
—
—
V
CC
– 0.010
V
CC
– 0.800
0.800
0.400
0.200
0.400
100
50
Max.
—
V
CC
V
CC
– 0.1
V
CC
V
CC
– 0.65
1.00
—
—
—
120
60
Unit
mV
V
V
V
V
V
V
V
V
Ω
Ω
No Load
No Load
No Load
100Ω Load
(3)
50Ω Load
(4)
(SY55851)
50Ω Load
(5)
(SY55851A)
Condition
NOTES:
1. The DC parameters are guaranteed after thermal equilibrium has been established.
2. Actual voltage levels and differential swing will depend on customer termination scheme. Refer to the “CML Termination” diagram for more details.
3. Applies to SY55851: 200Ω termination resistor across Q and /Q. See
Figure 3a.
4. Applies to the SY55851. See
Figure 3c.
5. Applies to the SY55851A: 100Ω termination resistor across Q and /Q. See
Figure 3b.
5
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