LV11B Series 3.3 V
LVDS Clock Oscillators
May 2006
• Pletronics’ LV11B Series is a quartz crystal
controlled precision square wave generator
with an LVDS output.
• Solder pad compatible with many 9x14 Plastic
J lead packages.
• FR4 base with a mechanical metal cover.
• Tape and Reel or Tube packaging is available.
•
•
•
•
•
1 to 700 MHz
9.9mm x 13.97mm ‘B’ package
Enable/Disable Function on pad 2
Does NOT permit “wired-OR” of outputs
Low Jitter
Pletronics Inc. certifies this device is in accordance with the
RoHS 6/6 (2002/95/EC) and WEEE (2002/96/EC) directives.
Pletronics Inc. guarantees the device does not contain the following:
Cadmium, Hexavalent Chromium, Lead, Mercury, PBB’s, PBDE’s
Weight of the Device: 2.18 grams or .82 grams or 1.51 grams
Moisture Sensitivity Level: 1 As defined in J-STD-020C
Second Level Interconnect code: e4
Absolute Maximum Ratings:
Parameter
V
CC
Supply Voltage
Vi
Vo
Input Voltage
Output Voltage
Unit
-0.5V to +7.0V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CC
+ 0.5V
Thermal Characteristics
The maximum die or junction temperature is 155
o
C
The thermal resistance junction to board is 60 to 100
o
C/Watt depending on the solder pads, ground plane
and construction of the PCB.
Product information is current as of publication date. The product conforms
to specifications per the terms of the Pletronics standard warranty. Production
processsing does not necessarily include testing of all parameters.
Copyright © 2005, 2006, Pletronics Inc.
LV11B Series 3.3 V
LVDS Clock Oscillators
May 2006
Part Number:
LV11
45
B
E
V - 125.0M
-XX
Internal code or blank
Frequency in MHz
Supply Voltage V
CC
V
= 3.3V + 10%
_
Optional Enhanced OTR
E
= Temperature range -40 to 85
o
C
Series Model
Frequency Stability
45
= + 50 ppm
_
44
= + 25 ppm
_
20
= + 20 ppm
_
Series Model
Part Marking:
PLE
LV11B
FFFFFM
C
YMDXX
or
LV11BX
FFFFFM
PLE
XX
C
YYWWXX
LF
Legend:
PLE
= Pletronics
= Frequency in MHz
FFFFFM
YMD or YYWW
= Date of Manufacture (Year - month - day or year and week)
All other marking is internal factory codes
Specifications such as frequency stability, supply voltage and operating temperature range, etc.
are not identified from the marking. External packaging labels and packing list will correctly
identify the ordered Pletronics part number.
www.pletronics.com
425-776-1880
2
LV11B Series 3.3 V
LVDS Clock Oscillators
May 2006
Electrical Specification for 3.30V +10% over the specified temperature range
_
Item
Frequency Range
Frequency Accuracy “45"
“44"
“20"
Output Waveform
Output High Level
Output Low Level
Differential Output (V
OD
)
Output Offset Voltage (V
OS
)
Differential Output Error (dV
OS
)
Output Symmetry
Output T
RISE
and T
FALL
Jitter
--
0.90
250
1.125
--
45
300
400
-
-
Vcc Supply Current
Enable/Disable Internal Pull-up
V disable
V enable
Enable
Disable time
Start up time
Operating Temperature Range
-
50
-
2.0
-
-
-
0
-40
Storage Temperature Range
-55
Min
1
-50
-25
-20
Max
700
+50
+25
+20
LVDS
1.60
--
450
1.375
50
55
700
900
0.2
2.8
90
-
0.8
-
100
100
5
+70
+85
+125
mA
Kohm
Volts
Volts
nS
nS
mS
o
o
o
Unit
MHz
ppm
Condition
For all supply voltages, load changes, aging for 1
year, shock, vibration and temperatures
Volts
Volts
mVolts
Volts
mVolts
%
pS
pS
pS RMS
Referenced to 50% of amplitude or crossing point
> 80 MHz
< 80 MHz
Vth is 20% and 80% of waveform
> 80 MHz
See load circuit
R1 = 50 ohms
Measured from 12KHz to 20MHz from Fnominal
Measured from 10Hz to 1MHz from Fnominal
> 80 MHz
Includes current of properly
terminated device
To Vcc (equivalent resistance)
Referenced to Ground
Time for output to reach a logic state
Time for output to reach a high Z state
> 80 MHz
Measured from the time
Vcc = 3.0V
C
C
C
Standard Temperature Range
Extended Temperature Range
“E” Option
Specifications with Pad 2 E/D open circuit
www.pletronics.com
425-776-1880
3
LV11B Series 3.3 V
LVDS Clock Oscillators
May 2006
Typical Phase-Noise Response
0
-20
-40
dBc/Hz
-60
-80
-100
-120
-140
-160
10
1,000
100,000
10,000,000
Frequency (Hz)
Load Circuit
Test Waveform
Symmetry
Vhigh
80%
50%
20%
Vlow
Trise
Tfall
Out
Out*
www.pletronics.com
425-776-1880
4
LV11B Series 3.3 V
LVDS Clock Oscillators
May 2006
Reliability
: Environmental Compliance
Parameter
Mechanical Shock
Vibration
Solderability
Thermal Shock
Condition
MIL-STD-883 Method 2002, Condition B
MIL-STD-883 Method 2007, Condition A
MIL-STD-883 Method 2003
MIL-STD-883 Method 1011, Condition A
ESD Rating
Model
Human Body Model
Charged Device Model
Minimum Voltage
1500
1000
Conditions
MIL-STD-883 Method 3115
JESD 22-C101
Package Labeling
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Courier New
Bar code is 39-Full ASCII
Label is 1" x 2.6" (25.4mm x 66.7mm)
Font is Arial
Layout and application information
Recommend connecting Pad 1 and Pad 2 together to permit the design to accept Enable/Disable on both
input pads
For Optimum Jitter Performance, Pletronics recommends:
•
a ground plane under the device
•
no large transient signals (both current and voltage) should be routed under the device
•
do not layout near a large magnetic field such as a high frequency switching power supply
•
do not place near piezoelectric buzzers or mechanical fans.
www.pletronics.com
425-776-1880
5