D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
MC33567
Dual Linear Controller
for High Current
Voltage Regulation
The MC33567 Dual Linear Power Supply Controller is designed to
facilitate power management for motherboard applications where
reliable regulation of high current supply planes is required. It
provides the Drive, Sense and Control signals to interface two
external, N−channel MOSFETs for regulating two different supply
planes. Undervoltage short circuit detection places the operation of the
system into a protected mode pending removal of the short.
Features
http://onsemi.com
MARKING
DIAGRAM
SO−8
D SUFFIX
CASE 751
M567x
ALYW
•
Two Independent Regulated Supplies
•
MC33567−1: 1.515 V
−
Supply for GTL and AGP Planes
•
•
•
•
•
•
•
8
1
1.818 V
−
Supply for I/O Plane and Memory
Termination
MC33567−2: Dual 2.525 V Supplies for Clock and Memory
MC33567−3: 2.3 V
−
Voltage Supply
1.2 V
−
Voltage Supply
Undervoltage Short Circuit Protection
Supply Undervoltage Detection
Drive Capability for N−Channel MOSFETs
Bypass Function for 3.3 V AGP Card Detection
Pb−Free Package May be Available. The G−Suffix Denotes a
Pb−Free Lead Finish
x
A
L
Y
W
= 1, 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
DRV1 1
SENSE1
2
8
7
6
5
V
CC
DRV2
SENSE2
SHDN2
Applications
SHDN1 3
GND
4
•
Motherboards
•
Dual Power Supplies
V
CC
3.3 V
4
GND
3
SHDN1
8
V
CC
66 kW
Startup &
Undervoltage
Shutdown
REF
V
CC
Control
2
SENSE1
V
out1
1
DRV1
3.3 V
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 283 of this data sheet.
+
+
8.5 V
−
−
UVLO
V
in
Bypass On (MC33567−1 only)
V
CC
3.3 V
66 kW
REF
V
CC
Startup &
Undervoltage
Shutdown
REF
Control
6
SENSE2
7
DRV2
3.3 V
C
L
5
SHDN2
V
out2
C
L
Figure 1. Simplified Block Diagram
©
Semiconductor Components Industries, LLC, 2003
December, 2003
−
Rev. 3
273
Publication Order Number:
MC33567/D
MC33567
PIN ASSIGNMENTS AND FUNCTIONS
PIN #
1
2
3
4
5
6
7
8
PIN NAME
DRV1
SENSE1
SHDN1
GND
SHDN2
SENSE2
DRV2
V
CC
TTL high level turns on regulation for gate 2. (Internal pull−up to 3.3 V)
Sense 2 line. Sense load voltage and provides feedback to regulator.
Gate 2 drive. Saturates external FET in bypass mode (MC33567−1 only).
Is internally clamped to ground in power down mode.
Supply voltage for operation and gate drive output
−
typically 12 V.
PIN DESCRIPTION
Gate 1 drive. Is internally clamped to ground in power down mode.
Sense 1 line. Sense load voltage and provides feedback to regulator.
TTL high level turns on regulation for gate 1. (Internal pull−up to 3.3 V)
MAXIMUM RATINGS
(Notes 1, 2 and 3)
Rating
Supply Voltage
SHUTDOWN Voltage
Operating Ambient Temperature
Operating Junction Temperature
Lead Temperature (Soldering, 10 seconds)
Storage Temperature Range
Package Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Symbol
V
CC
V
SHDN
T
A
T
J
T
L
T
stg
R
θJA
(Note 2)
R
θJC
Value
12.5
V
CC
0 to 80
−5.0
to 125
300
−55
to 150
159
28
Unit
Vdc
Vdc
°C
°C
°C
°C
°C/W
°C/W
1. ESD Ratings
ESD Machine Model protection up to 200 V, class B.
ESD Human Body Model protection up to 2000 V, class 2.
2. Minimum pad test board with 5 MIL wide and 2.8 MIL thick copper traces1 inch long.
3. All characterizing done with MTD3055VL N−Channel MOSFETs.
http://onsemi.com
274
MC33567
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 12 V, V
SHDN1
= V
SHDN2
= 2.0 V, T
A
= 0°C to 80°C, typical values shown are for T
J
= 25°C unless otherwise noted.)
Characteristic
Supply Voltage
Quiescent Current
V
SHDN1
= V
SHDN2
= 0 V
V
SHDN1
= V
SHDN2
= 2.0 V
Symbol
V
cc
I
qL
I
qH
Min
9.0
−
−
Typ
12
5.8
6.3
Max
12.5
9.0
10
Unit
V
mA
UNDERVOLTAGE LOCKOUT
Undervoltage Lockout Threshold Voltage (V
CC
Increasing)
Hysteresis Voltage (V
CC
Decreasing)
UVLO
UVLO
Vhys
7.0
0.2
8.5
0.5
9.0
0.9
V
V
DRIVE OUTPUTS
Drive Output Voltage (Gate to Ground)
Drive Output Source Current (T
J
= 25°C)
Gate Drive Output Sink Current (V
sense
= 0 V, T
J
= 25°C)
V
drv
I
pkdrv
I
sink
−
10
4.0
10.5
20
7.0
−
30
10
V
mA
mA
SHUTDOWN INPUTS
Shutdown Threshold Voltage (Drive output on to off, ramp V
SHDN
to 0 V)
Shutdown Threshold Hysteresis (Drive output off to on)
Shutdown Disable Time (Drive output on to off, ramp V
SHDN
to 0 V)
Shutdown Input Current (V
SHDN
= 0 V)
SHDN
Vth
SHDN
hys
SHDN
tdis
I
SHDN
0.8
50
−
−
1.13
130
0.5
−50
1.3
200
2.0
−
V
mV
ms
mA
SHORT CIRCUIT
Short Circuit/Undervoltage Detect Threshold
(Load current increased until output voltage drops activating hiccup mode)
Drive Output Response Time to short circuit (Ramp down V
sense
to 0 V)
Drive Output On Time in hiccup mode (V
sense
= 0 V)
Drive Output Off Time in hiccup mode (V
sense
= 0 V)
SC
uvd
SC
td
SC
ton
SC
toff
70
200
0.5
20
75
325
0.97
47.7
80
500
1.5
60
%Vout
ms
ms
ms
OUTPUT REGULATION
Regulator Output Voltage (V
in
= 3.3 V, I
L
= 5.0 mA to 1.3 A)
MC33567−1
Output 1
Output 2
MC33567−2
Output 1
Output 2
MC33567−3
Output 1
Output 2
Output Voltage Regulation (I
L
= 5.0 mA to 1.3 A)
V
V
out1
V
out2
V
out1
V
out2
V
out1
V
out2
V
reg%
1.773
1.477
2.462
2.462
2.243
1.170
−2.5
1.818
1.515
2.525
2.525
2.300
1.200
−
1.864
1.553
2.589
2.589
2.358
1.230
+2.5
%
http://onsemi.com
275
MC33567
OPERATING DESCRIPTION
Introduction
The MC33567 series is a family of Dual Linear FET
Controllers designed for Power Management applications
where high current, voltage regulation is needed. Some
computer applications include:
•
1.2 V
−
Power Supply
•
1.515 V
−
AGP (Advanced Graphic Port) and GTL+
(Gunning Transistor Logic
−
Intel’s electrical bus
technology)
•
1.818 V
−
I/O planes on motherboards
•
2.3 V
−
Power Supply
•
2.525 V
−
Clock and memory
The MC33567 provides tight output voltage regulation,
(V
out
), and incorporates individual SHDN controls for each
FET controller and voltage protection by sensing the output
voltage.
Output:
Listed below are the SHDN threshold voltage levels and
the corresponding regulator output voltages:
1. If the SHDN pin is left open, the output voltage is set
to its regulated value.
2. If a voltage less than 0.8 V is applied to the SHDN pin,
the output voltage is set to 0 V.
3. If a voltage greater than 1.3 V and less than 4.1 V is
applied to the SHDN pin, the output voltage is set to its
regulated voltage.
4. If the SHDN voltage is pulled above 4.1 V, the
MC33567 enters a V
in
bypass mode. In this mode, the
MOSFET is fully enhanced and the output voltage is
the MOSFET drain voltage (V
in
) minus the MOSFET
drain−source on voltage V
DS(on)
. This feature is only
available on REGULATOR 2 of the MC33567−1.
Table 1 summarizes the output voltage options and its
relationship with V
SHDN
.
Table 1. Logic Table for SHDN Pin
Device
MC33567−1
REGULATOR 1
V
SHDN
(V)
No Connect
t0.8
V
u1.3
V
No Connect
t0.8
V
1.3 V
t
V
SHDN
t
4.1 V
u
4.1 V
V
out
(V)
1.818 V
0V
1.818 V
1.515 V
0V
1.515 V
V
in
−V
DS(on)
(Bypass Mode)
The MC33567 provides tight output voltage regulation
from one or two supply voltages using 2 external N−Channel
MOSFETs. Each controller operates independently and
regulates the output voltage to a predetermined level (1.2 V,
1.515 V 1.818 V, 2.3 V or 2.525 V). In addition, regulator 2
of the MC33567−1 incorporates a V
in
bypass mode on which
the external FET is fully enhanced.
Shutdown:
REGULATOR 2
The regulated outputs of the MC33567 can be disabled
with the use of the SHDN pin. It also determines the output
voltage level. SHDN can be controlled externally from
board signals like the AGP or GTL+ as shown in Figure 3.
3.3 V (V
in
)
AGP
Card Type
Detection
12 V (V
CC
)
3.3 V
10 kW
1
2
3
4
8
7
MC33567−2
REGULATOR 1 &
REGULATOR 2
MC33567−3
REGULATOR 1
No Connect
t0.8
V
u1.3
V
No Connect
t0.8
V
u1.3
V
No Connect
t0.8
V
u
1.3 V
2.525 V
0V
2.525 V
2.3 V
0V
2.3 V
1.2 V
0V
1.2 V
AGP
Card
Voltage
V
out
or V
in
*
REGULATOR 2
Undervoltage Detection:
MC33567
6
5
DRV2
SENSE2
SHDN2
*V
in
while on bypass mode (MC33567−1 only)
Figure 3. 1.5 V/3.3 V AGP Card Detection
If V
out
drops below 75% of the regulated threshold for
greater than 250
µs
or a short circuit condition is present, that
output will go into short circuit or Hiccup Mode. While in
Hiccup mode, the output is turned ON for 1.0 ms and OFF
for 40 ms for a duty cycle of 1:41 as shown in Figure 4. This
mode will continue as long as the fault is present. Once the
fault is removed, the regulator will resume normal
operation.
1 ms
40 ms
Figure 4. Hiccup Mode Duty Cycle
http://onsemi.com
276
京公网安备 11010802033920号
EEWORLD
