A1010B-PGG84M datasheet, PDF - EEWORLD Datasheet

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A1010B-PGG84M: DescriptionField Programmable Gate Array, 295 CLBs, 1200 Gates, 37MHz, CMOS, CPGA84, CERAMIC, PGA-84; CategoryProgrammable logic devices Programmable logic; File Size166KB，24 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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A1010B-PGG84M Overview

Field Programmable Gate Array, 295 CLBs, 1200 Gates, 37MHz, CMOS, CPGA84, CERAMIC, PGA-84

A1010B-PGG84M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	PGA,
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Other features	MAX 57 I/OS
maximum clock frequency	37 MHz
Combined latency of CLB-Max	5.5 ns
JESD-30 code	S-CPGA-P84
JESD-609 code	e4
length	27.94 mm
Configurable number of logic blocks	295
Equivalent number of gates	1200
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	295 CLBS, 1200 GATES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.318 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD OVER NICKEL
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	27.94 mm

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ACT

™

1 Series FPGAs

Fe atur es

• 5V and 3.3V Families fully compatible with JEDEC

specifications

• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)

• Replaces up to 50 TTL Packages

• Replaces up to twenty 20-Pin PAL Packages

• Design Library with over 250 Macro Functions

• Gate Array Architecture Allows Completely Automatic

Place and Route

• Up to 547 Programmable Logic Modules

• Up to 273 Flip-Flops

• Data Rates to 75 MHz

• Two In-Circuit Diagnostic Probe Pins Support Speed

Analysis to 25 MHz

• Built-In High Speed Clock Distribution Network

• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)

• Nonvolatile, User Programmable

• Fabricated in 1.0 micron CMOS technology

De scrip tion

A security fuse may be programmed to disable all further

programming and to protect the design from being copied or

reverse engineered.

Pr od uc t F a mi l y P r o fi le

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

Logic Modules

Flip-Flops (maximum)

Routing Resources

Horizontal Tracks/Channel

Vertical Tracks/Column

PLICE Antifuse Elements

User I/Os (maximum)

Packages:

A1010B

A10V10B

1,200

3,000

295

147

112,000

44 PLCC

68 PLCC

A1020B

A10V20B

2,000

6,000

547

273

186,000

The ACT™ 1 Series of field programmable gate arrays

(FPGAs) offers a variety of package, speed, and application

combinations. Devices are implemented in silicon gate,

1-micron two-level metal CMOS, and they employ Actel’s

PLICE

antifuse technology. The unique architecture offers

gate array flexibility, high performance, and instant

turnaround through user programming. Device utilization is

typically 95 to 100 percent of available logic modules.

ACT 1 devices also provide system designers with unique

on-chip diagnostic probe capabilities, allowing convenient

testing and debugging. Additional features include an on-chip

clock driver with a hardwired distribution network. The

network provides efficient clock distribution with minimum

skew.

The user-definable I/Os are capable of driving at both TTL

and CMOS drive levels. Available packages include plastic

and ceramic J-leaded chip carriers, ceramic and plastic quad

flatpacks, and ceramic pin grid array.

44 PLCC

68 PLCC

84 PLCC

100 PQFP 100 PQFP

80 VQFP 80 VQFP

84 CPGA 84 CPGA

84 CQFP

75 MHz

55 MHz

75 MHz

55 MHz

Performance

5 V Data Rate (maximum)

3.3 V Data Rate (maximum)

Note:

See Product Plan on page 1-286 for package availability.

Th e De s i g ne r an d De s i gn e r

A dv a n t a ge ™ Sy s t em s

The ACT 1 device family is supported by Actel’s Designer and

Designer Advantage Systems, allowing logic design

implementation with minimum effort. The systems offer

Microsoft

Windows

™

and X Windows

™

graphical user

interfaces and integrate with the resident CAE system to

provide a complete gate array design environment: schematic

capture, simulation, fully automatic place and route, timing

verification, and device programming. The systems also

include the ACTmap

™

VHDL optimization and synthesis tool

and the ACTgen

™

Macro Builder, a powerful macro function

generator for counters, adders, and other structural blocks.

April 1996

1-283

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