a
FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP or 44-Pin PLCC Package
Plug-In Replacement for BT101
Power Dissipation: 400 mW
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing
SPEED GRADES
80 MHz
50 MHz
30 MHz
GENERAL DESCRIPTION
CMOS
80 MHz, Triple 8-Bit Video DAC
ADV101*
FUNCTIONAL BLOCK DIAGRAM
V
AA
FS
ADJUST
V
REF
REFERENCE
AMPLIFIER
COMP
ADV101
CLOCK
R0
R7
8
RED
REGISTER
8
DAC
IOR
PIXEL
INPUT
PORT
G0
G7
8
GREEN
REGISTER
8
DAC
IOG
B0
8
B7
BLUE
REGISTER
8
DAC
IOB
REF WHITE
BLANK
SYNC
CONTROL
REGISTER
SYNC
CONTROL
I
SYNC
GND
The ADV101 is a digital-to-analog video converter on a single
monolithic chip. The part is specifically designed for high reso-
lution color graphics and video systems. It consists of three,
high speed, 8-bit, video D/A converters (RGB); a standard TTL
input interface and high impedance, analog output, current
sources.
The ADV101 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include sync, blank and reference white. A
single +5 V supply, an external 1.23 V reference and pixel clock
input are all that are required to make the part operational.
The ADV101 is capable of generating RGB video output sig-
nals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV101 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation. The part is packaged in both a 0.6", 40-pin
plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier,
PLCC.
*ADV
is a registered trademark of Analog Devices Inc.
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Compatible with a wide variety of high resolution color
graphics video systems.
3. Guaranteed monotonic with a maximum differential nonlin-
earity of
±
0.5 LSB. Integral nonlinearity is guaranteed to be
a maximum of
±
1 LSB.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADV101–SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity, INL
Differential Nonlinearity, DNL
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN2
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on IOR, IOB
Blank Level on IOG
Sync Level on IOG
LSB Size
DAC to DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT2
Output Capacitance, C
OUT2
VOLTAGE REFERENCE
Voltage Reference Range, V
REF
Input Current, I
VREF
POWER REQUIREMENTS
V
AA
I
AA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Glitch Impulse
2, 3
DAC Noise
2, 3, 4
Analog Output Skew
8
±
1
±
0.5
±
5
Binary
2
0.8
±
1
10
15
22
17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
9.5
0
50
69.1
2
–1
+1.4
100
30
1.14/1.26
+10
5
125
100
0.5
625
500
50
200
2
(V
AA
= +5 V 5%; V
REF
= +1.235 V; R
L
= 37.5 , C
L
= 10 pF; R
SET
= 560 . I
SYNC
connected to IOG. All Specifications T
MIN
to T
MAX1
unless otherwise noted.)
Test Conditions/Comments
All Versions Units
Bits
LSB max
LSB max
Guaranteed Monotonic
% Gray Scale max Max Gray Scale Current: IOG = (V
REF
* 12,082/R
SET
) mA
Max Gray Scale Current:
IOR, IOB = (V
REF
* 8,627/R
SET
) mA
V min
V max
µA
max
pF max
mA min
mA max
mA min
mA max
mA min
mA max
mA min
mA max
µA
min
µA
max
mA min
mA max
µA
min
µA
max
µA
typ
% typ
V min
V max
kΩ typ
pF max
V min/V max
µA
typ
V nom
mA max
mA max
%/% max
mW max
mW max
pV secs typ
pV secs typ
ns max
V
IN
= 0.4 V or 2.4 V
Typically 19.05 mA
Typically 17.62 mA
Typically 1.44 mA
Typically 5
µA
Typically 7.62 mA
Typically 5
µA
I
OUT
= 0 mA
V
REF
= 1.235 V for Specified Performance
Typically 80 mA: 80 MHz Parts
Typically 70 mA: 50 MHz & 35 MHz Parts
Typically 0.12%/%: f = 1 kHz, COMP = 0.1
µF
Typically 400 mW: 80 MHz Parts
Typically 350 mW: 50 MHz & 30 MHz Parts
Typically 1 ns
NOTES
1
Temperature Range (T
MIN
to T
MAX
); 0°C to +70°C.
2
Sample tested at +25°C to ensure compliance.
3
TTL input values are 0 to 3 volts, with input rise/fall times
≤
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4
This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.
–2–
REV. B
ADV101
TIMING CHARACTERISTICS
Parameter
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8 3
80 MHz Version
80
3
2
12.5
4
4
30
20
3
12
1
(V
AA
= +5 V
5%; V
REF
= +1.235 V; R
L
= 37.5 , C
L
= 10 pF; R
SET
= 560 .
I
SYNC
connected to IOG. All Specifications T
MIN
to T
MAX2
unless otherwise noted.)
30 MHz Version
30
8
2
33.3
9
9
30
20
3
15
Units
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns typ
Conditions/Comments
Clock Rate
Data & Control Setup Time
Data & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Transition Time
50 MHz Version
50
6
2
20
7
7
30
20
3
15
NOTES
1
TTL input values are 0 to 3 volts, with input rise/fall times
≤3
ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
puts. See timing notes in Figure 1.
2
Temperature range (T
MIN
to T
MAX
): 0°C to +70°C.
3
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
t
3
t
4
CLOCK
t
5
t
1
DIGITAL INPUTS
(R0–R7, G0–G7, B0–B7;
SYNC, BLANK,
REF WHITE)
DATA
t
2
t
6
t
8
ANALOG OUTPUTS
(IOR, IOG, IOB, I
SYNC
)
t
7
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS
OF FULL TRANSITION.
Figure 1. Video Input/Output Timing
REV. B
–3–
ADV101
ABSOLUTE MAXIMUM RATINGS
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply
Ambient Operating
Temperature
Output Load
Reference Voltage
Symbol
V
AA
T
A
R
L
V
REF
Min
4.75
0
1.14
Typ
5.00
Max
5.25
+70
Units
Volts
°C
Ω
Volts
37.5
1.235 1.26
V
AA
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . GND – 0.5 V to V
AA
+ 0.5 V
Ambient Operating Temperature (T
A
) . . . . . . . . 0°C to +70°C
Storage Temperature (T
S
) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . +150°C
Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C
IOR, IOB, IOG, I
SYNC
to GND
2
. . . . . . . . . . . . . . 0 V to V
AA
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Analog output short circuit to any power supply or common can be of an indefinite
duration.
ORDERING GUIDE
1
Package
Option
2
Plastic DIP
(N-40A)
PLCC
3
(P-44A)
80 MHz
Speed
50 MHz
30 MHz
ADV101KN80 ADV101KN50 ADV101KN30
ADV101KP80
ADV101KP50
ADV101KP30
NOTES
1
All devices are specified for 0°C to +70°C operation.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier.
3
PLCC: Plastic Leaded Chip Carrier (J-lead).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP
G4 1
R7 2
R6 3
R5 4
R4 5
B7 6
B6 7
B5 8
B4 9
V
AA
10
GND 11
B0 12
B1 13
B2 14
B3 15
CLOCK 16
R0 17
R1 18
R2 19
R3 20
40 G5
WARNING!
ESD SENSITIVE DEVICE
PLCC
GND
GND
V
AA
V
AA
B3
B2
B0
B5
41
39 G6
38 G7
37 BLANK
36 SYNC
35 GND
6
5
B1
4
3
2
1
44
43
42
B4
40
CLOCK
R0
R1
B6
39 B7
38 R4
37 R5
36 R6
35 R7
34 G4
33 G5
32 G6
31 G7
30 BLANK
29 SYNC
28
7
8
9
ADV101
TOP VIEW
(NOT TO SCALE)
34 IOB
33 IOR
32 IOG
31 I
SYNC
30 V
AA
29 GND
28 FS ADJUST
27 V
REF
26 COMP
25 REF WHITE
R2 10
R3 11
G0 12
G1 13
G2 14
G3 15
REF WHITE 16
COMP 17
ADV101
TOP VIEW
(Not to Scale)
18
19
20
21
22
23
24
25
26
27
GND
IOR
GND
FS ADJUST
V
REF
23 G2
22 G1
21 G0
I
SYNC
GND
V
AA
V
AA
IOG
IOB
24 G3
–4–
REV. B
ADV101
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
BLANK
Function
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. The
BLANK
signal is latched on the rising edge of CLOCK. While
BLANK
is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are ignored.
Composite sync control input (TTL compatible). A logical zero on the
SYNC
input; switches off a 40 IRE cur-
rent source on the I
SYNC
output.
SYNC
does not override any other control or data input, therefore, it should
only be asserted during the blanking interval.
SYNC
is latched on the rising edge of CLOCK.
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC,
BLANK
and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB out-
puts to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7) REF WHITE is latched
on the rising edge of clock.
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the regular
PCB power or ground plane.
Red, green and blue current outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75
Ω
coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
Sync current output. This high impedance current source can be directly connected to the IOG output. This al-
lows sync information to be encoded onto the green channel. I
SYNC
does not output any current while
SYNC
is
at logical zero. The amount of current output at I
SYNC
while
SYNC
is at logical one is given by:
I
SYNC
(mA) = 3,455
×
V
REF
(V)/R
SET
(Ω)
If sync information is not required on the green channel, I
SYNC
should be connected to AGND.
Full-scale adjust control. A resistor (R
SET
) connected between this pin and GND, controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between R
SET
and the full-scale output current on IOG (assuming I
SYNC
is connected to IOG)
is given by:
R
SET
(Ω) = 12,082
×
V
REF
(V)/IOG
(mA)
The relationship between R
SET
and the full-scale output current on IOR and IOB is given by:
IOR, IOB (mA) =
8,628
×
V
REF
(V)/
R
SET
(Ω)
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1
µF
ceramic capacitor
must be connected between COMP and V
AA
.
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an exter-
nal resistor divider network is not recommended. A 0.1
µF
decoupling ceramic capacitor should be connected
between V
REF
and V
AA
.
Analog power supply (5 V
±
5%). All V
AA
pins on the ADV101 must be connected.
Ground. All GND pins must be connected.
SYNC
CLOCK
REF WHITE
R0–R7,
G0–G7,
B0–B7
IOR, IOG, IOB
I
SYNC
FS ADJUST
COMP
V
REF
V
AA
GND
REV. B
–5–
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