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MT5C1009CW-55E/883C

Description
Standard SRAM, 128KX8, 55ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32
Categorystorage    storage   
File Size249KB,17 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C1009CW-55E/883C Overview

Standard SRAM, 128KX8, 55ns, CMOS, CDIP32, 0.600 INCH, CERAMIC, DIP-32

MT5C1009CW-55E/883C Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicross
Parts packaging codeDIP
package instructionDIP, DIP32,.6
Contacts32
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time55 ns
Other featuresTTL COMPATIBLE INPUTS/OUTPUTS; BATTERY BACKUP; LOW POWER STANDBY
I/O typeCOMMON
JESD-30 codeR-CDIP-T32
JESD-609 codee0
length40.64 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height4.3434 mm
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.125 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
SRAM
Austin Semiconductor, Inc.
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MT5C1009
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
Access Times: 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
32-Pin LCC (ECA)
4 3 2 1 32 31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
OPTIONS
• Timing
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
• 2V data retention/low power
• Radiation Tolerant (EPI)
MARKING
-15
-20
-25
-35
-45
-55*
-70*
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
A12
A14
A10
6
NC
V
CC
A15
CE2
NC
32-Pin Flat Pack (F)
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
A9
A11
OE
\
A10
CE1
\
DQ8
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
GENERAL DESCRIPTION
C
CW
EC
ECA
F
DCJ
SOJ
L
E
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory
applications, this device offers chip enable (CE\) and output
enable (OE\) features. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The devices offer a reduced power standby mode when dis-
abled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1009
Rev. 5.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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