D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
a
FEATURES
3.0 s Acquisition Time to 0.01% max
Low Droop Rate: 1.0 mV/ms max
Sample/Hold Offset Step: 3 mV max
Aperture Jitter: 0.5 ns
Extended Temperature Range: –55 C to +125 C
Internal Hold Capacitor
Internal Application Resistors
12 V or 15 V Operation
Available in Surface Mount
APPLICATIONS
Data Acquisition Systems
Data Distribution Systems
Analog Delay & Storage
Peak Amplitude Measurements
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
High Speed, Precision
Sample-and-Hold Amplifier
AD585
FUNCTIONAL BLOCK DIAGRAM
DIP
LCC/PLCC Package
The AD585 is a complete monolithic sample-and-hold circuit
consisting of a high performance operational amplifier in series
with an ultralow leakage analog switch and a FET input inte-
grating amplifier. An internal holding capacitor and matched
applications resistors have been provided for high precision and
applications flexibility.
The performance of the AD585 makes it ideal for high speed
10- and 12-bit data acquisition systems, where fast acquisition
time, low sample-to-hold offset, and low droop are critical. The
AD585 can acquire a signal to
±
0.01% in 3
µs
maximum, and
then hold that signal with a maximum sample-to-hold offset of
3 mV and less than 1 mV/ms droop, using the on-chip hold
capacitor. If lower droop is required, it is possible to add a
larger external hold capacitor.
The high speed analog switch used in the AD585 exhibits
aperture jitter of 0.5 ns, enabling the device to sample full scale
(20 V peak-to-peak) signals at frequencies up to 78 kHz with
12-bit precision.
The AD585 can be used with any user-defined feedback net-
work to provide any desired gain in the sample mode. On-chip
precision thin-film resistors can be used to provide gains of +1,
–1, or +2. Output impedance in the hold mode is sufficiently
low to maintain an accurate output signal even when driving the
dynamic load presented by a successive-approximation A/D
converter. However, the output is protected against damage
from accidental short circuits.
The control signal for the HOLD command can be either active
high or active low. The differential HOLD signal is compatible
with all logic families, if a suitable reference level is provided. An
on-chip TTL reference level is provided for TTL compatibility.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
The AD585 is available in three performance grades. The JP
grade is specified for the 0°C to +70°C commercial temperature
range and packaged in a 20-pin PLCC. The AQ grade is speci-
fied for the –25°C to +85°C industrial temperature range and is
packaged in a 14-pin cerdip. The SQ and SE grades are speci-
fied for the –55°C to +125°C military temperature range and
are packaged in a 14-pin cerdip and 20-pin LCC.
PRODUCT HIGHLIGHTS
1. The fast acquisition time (3
µs)
and low aperture jitter
(0.5 ns) make it the first choice for very high speed data
acquisition systems.
2. The droop rate is only 1.0 mV/ms so that it may be used in
slower high accuracy systems without the loss of accuracy.
3. The low charge transfer of the analog switch keeps sample-to
hold offset below 3 mV with the on-chip 100 pF hold capaci-
tor, eliminating the trade-off between acquisition time and
S/H offset required with other SHAs.
4. The AD585 has internal pretrimmed application resistors for
applications versatility.
5. The AD585 is complete with an internal hold capacitor for
ease of use. Capacitance can be added externally to reduce
the droop rate when long hold times and high accuracy are
required.
6. The AD585 is recommended for use with 10- and 12-bit
successive-approximation A/D converters such as AD573,
AD574A, AD674A, AD7572 and AD7672.
7. The AD585 is available in versions compliant with MIL-STD-
883. Refer to the Analog Devices Military Products Databook
or current AD585/883B data sheet for detailed specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD585–SPECIFICATIONS
Model
Min
SAMPLE/HOLD CHARACTERISTICS
Acquisition Time, 10 V Step to 0.01%
20 V Step to 0.01%
Aperture Time, 20 V p-p Input,
HOLD
0 V
Aperture Jitter, 20 V p-p Input,
HOLD
0 V
Settling Time, 20 V p-p Input,
HOLD
0 V, to 0.01%
Droop Rate
Droop Rate T
MIN
to T
MAX
Charge Transfer
Sample-to-Hold Offset
Feedthrough
20 V p-p, 10 kHz Input
TRANSFER CHARACTERISTICS
Open Loop Gain
V
OUT
= 20 V p-p, R
L
= 2k
Application Resistor Mismatch
Common-Mode Rejection
V
CM
=
±
10 V
Small Signal Gain Bandwidth
V
OUT
= 100 mV p-p
Full Power Bandwidth
V
OUT
= 20 V p-p
Slew Rate
V
OUT
= 20 V p-p
Output Resistance (Sample Mode)
I
OUT
=
±
10 mA
Output Short Circuit Current
Output Short Circuit Duration
1
(typical @ +25 C and V
S
= 12 V or
HOLD
active unless otherwise noted)
Max
3
5
Min
AD585A
Typ
Max
3
5
35
0.5
0.5
1
Double Every 10°C
0.3
–3
3
0.5
15 V, and C
H
= Internal, A = +1,
AD585S
Typ
AD585J
Typ
Min
Max
3
5
Units
µs
µs
ns
ns
µs
mV/ms
pC
mV
mV
35
0.5
0.5
1
Doubles Every 10°C
0.3
–3
3
0.5
35
0.5
0.5
1
Doubles Every 10°C
0.3
–3
3
0.5
200,000
0.3
80
2.0
160
10
0.05
50
Indefinite
5
6
2
5
10
10
12
1.2
2.0
0.8
50
+5, –10.8
6
70
0
±
18
10
+5, –10.8
6
70
–25
1.4
1.6
1.2
2.0
80
200,000
0.3
80
2.0
160
10
0.05
50
Indefinite
2
3
2
5
10
10
12
1.4
1.6
1.2
2.0
0.8
50
±
18
10
+5, –10.8
6
70
–55
200,000
0.3
V/V
%
dB
2.0
160
10
0.05
50
Indefinite
2
3
2
50
2
MHz
kHz
V/µs
Ω
mA
ANALOG INPUT CHARACTERISTICS
Offset Voltage
Offset Voltage, T
MIN
to T
MAX
Bias Current
Bias Current, T
MIN
to T
MAX
Input Capacitance, f = 1 MHz
Input Resistance, Sample or Hold
20 V p-p Input, A = +1
DIGITAL INPUT CHARACTERISTICS
TTL Reference Output
Logic Input High Voltage
T
MIN
to T
MAX
Logic Input Low Voltage
T
MIN
to T
MAX
Logic Input Current (Either Input)
POWER SUPPLY CHARACTERISTICS
Operating Voltage Range
Supply Current, R
L
=
∞
Power Supply Rejection, Sample Mode
TEMPERATURE RANGE
Specified Performance
PACKAGE OPTIONS
Cerdip (Q-14)
LCC (E-20A)
PLCC (P-20A)
3, 4
20
10
10
12
1.4
mV
mV
nA
nA
pF
Ω
1.6
V
V
0.7
50
±
18
10
V
µA
V
mA
dB
°C
+70
+85
AD585AQ
+125
AD585SQ
AD585SE
AD585JP
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels.
All min and max specifications are
guaranteed, although only those shown in
NOTES
1
Maximum input signal is the minimum supply minus a headroom voltage of 2.5 V.
2
Not tested at –55°C.
3
E = Leadless Ceramic Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip.
4
For AD585/883B specifications, refer to Analog Devices Military Products Databook.
boldface
are tested on all production units.
–2–
REV. A
AD585
ABSOLUTE MAXIMUM RATINGS
Supplies (+V
S
, –V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 18 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
V
S
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
V
S
R
IN
, R
FB
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
V
S
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering) . . . . . . . . . . . . . . . . . . . 300°C
Output Short Circuit to Ground . . . . . . . . . . . . . . . . Indefinite
TTL Logic Reference Short
Circuit to Ground . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Figure 2. Acquisition Time vs. Hold Capacitance
(10 V Step to 0.01%)
REV. A
–3–
AD585
SAMPLED DATA SYSTEMS
In sampled data systems there are a number of limiting factors
in digitizing high frequency signals accurately. Figure 9 shows
pictorially the sample-and-hold errors that are the limiting fac-
tors. In the following discussions of error sources the errors will
be divided into the following groups: 1. Sample-to-Hold Transi-
tion, 2. Hold Mode and 3. Hold-to-Sample Transition.
f
MAX
2
=
π
(
Aperture Jitter
)
–(
N
+
1)
For an application with a 10-bit A/D converter with a 10 V full
scale to a 1/2 LSB error maximum.
f
MAX
=
2
–(10
+
1)
–9
π
(0.5
×
10 )
f
MAX
=
310.8
kHz.
For an application with a 12-bit A/D converter with a 10 V full
scale to a 1/2 LSB error maximum:
f
MAX
=
2
–(12
+
1)
–9
π
(0.5
×
10 )
f
MAX
=
77.7
kHz.
Figure 9. Pictorial Showing Various S/H Characteristics
SAMPLE-TO-HOLD TRANSITION
Figure 11 shows the entire range of errors induced by aperture
jitter with respect to the input signal frequency.
The aperture delay time is the time required for the sample-and-
hold amplifier to switch from sample to hold. Since this is effec-
tively a constant then it may be tuned out. If however, the
aperture delay time is not accounted for then errors of the mag-
nitude as shown in Figure 10 will result.
Figure 11. Aperture Jitter Error vs. Frequency
Sample-to-hold offset is caused by the transfer of charge to the
holding capacitor via the gate capacitance of the switch when
switching into hold. Since the gate capacitance couples the
switch control voltage applied to the gate on to the hold capaci-
tor, the resulting sample-to-hold offset is a function of the logic
level .
Figure 10. Aperture Delay Error vs. Frequency
To eliminate the aperture delay as an error source the sample-
to-hold command may be advanced with respect to the input
signal .
Once the aperture delay time has been eliminated as an error
source then the aperture jitter which is the variation in aperture
delay time from sample-to-sample remains. The aperture jitter is
a true error source and must be considered. The aperture jitter
is a result of noise within the switching network which modu-
lates the phase of the hold command and is manifested in the
variations in the value of the analog input that has been held.
The aperture error which results from this jitter is directly re-
lated to the dV/dT of the analog input.
The error due to aperture jitter is easily calculated as shown be-
low. The error calculation takes into account the desired accu-
racy corresponding to the resolution of the N-bit A/D converter.
The logic inputs were designed for application flexibility and,
therefore, a wide range of logic thresholds. This was achieved by
using a differential input stage for HOLD and
HOLD.
Figure 1
shows the change in the sample-to-hold offset voltage based
upon an independently programmed reference voltage. Since
the input stage is a differential configuration, the offset voltage
is a function of the control voltage range around the pro-
grammed threshold voltage.
The sample-to-hold offset can be reduced by adding capacitance
to the internal 100 pF capacitor and by using
HOLD
instead of
HOLD. This may be easily accomplished by adding an external
capacitor between Pins 7 and 8. The sample-to-hold offset is
then governed by the relationship:
S/H Offset
(V )
=
Charge
(
pC
)
C
H
Total
(
pF
)
–4–
REV. A
京公网安备 11010802033920号
EEWORLD
