NC7SZ74 TinyLogic UHS D-Type Flip-Flop with Preset and Clear
July 2001
Revised January 2005
NC7SZ74
TinyLogic
UHS D-Type Flip-Flop with Preset and Clear
General Description
The NC7SZ74 is a single D-type CMOS Flip-Flop with pre-
set and clear from Fairchild’s Ultra High Speed Series of
TinyLogic
in the space saving US8 package. The device
is fabricated with advanced CMOS technology to achieve
ultra high speed with high output drive while maintaining
low static power dissipation over a very broad V
CC
operat-
ing range. The device is specified to operate over the
1.65V to 5.5V V
CC
range. The inputs and output are high
impedance when V
CC
is 0V. Inputs tolerate voltages up to
7V independent of V
CC
operating voltage.
The signal level applied to the D input is transferred to the
Q output during the positive going transition of the CLK
pulse.
Features
s
Space saving US8 surface mount package
s
MicroPak
Pb-Free leadless package
s
Ultra High Speed; t
PD
2.6 ns Typ into 50 pF at 5V V
CC
s
High Output Drive;
±
24 mA at 3V V
CC
s
Broad V
CC
Operating Range; 1.65V to 5.5V
s
Power down high impedance inputs/output
s
Overvoltage tolerant inputs facilitate 5V to 3V translation
s
Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Number
Package
Number
Code
Top Mark
SZ74
N9
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
Package Description
Supplied As
NC7SZ74K8X MAB08A
NC7SZ74L8X MAC08A
Pb-Free package per JEDEC J-STD-020B.
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500499
www.fairchildsemi.com
NC7SZ74
Logic Symbol
IEEE/IEC
Connection Diagrams
Pin Descriptions
Pin Names
D
CK
CLR
Q, Q
PR
Description
Data Input
Clock Pulse Input
Direct Clear Input
Flip-Flop Output
Direct Preset Input
(Top View)
Pin One Orientation Diagram
Truth Table
Inputs
CLR
L
H
L
H
H
H
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
CK
X
X
X
Outputs
Function
Q
L
H
H
L
H
Q
n
Q
H
L
H
H
L
Q
n
Clear
Preset
—
—
—
No Change
Pad Assignments for MicroPak
AAA represents Product Code Top Mark - see ordering code
Note:
Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
↑
↑
↓
H
=
HIGH Logic Level
L
=
LOW Logic Level
Q
n
=
No change in data
Z
=
High Impedance
X
=
Immaterial
↑ =
Rising Edge
↓ =
Falling edge
(Top Thru View)
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2
NC7SZ74
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
DC Input Diode Current (I
IK
)
V
IN
<
0V
DC Output Diode Current (I
OK
)
V
OUT
<
0V
DC Output (I
OUT
) Source/Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
Junction Temperature under Bias (T
J
)
Junction Lead Temperature (T
L
)
(Soldering, 10 seconds)
Power Dissipation (P
D
) @
+
85
°
C
260
°
C
250 mW
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
−
50 mA
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
150
°
C
Recommended Operating
Conditions
(Note 2)
Power Supply
Operating (V
CC
)
Data Retention
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Active State
3-STATE
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
1.8V, 2.5V
±
0.2V
V
CC
=
3.3V
±
0.3V
V
CC
=
5.5V
±
0.5V
Operating Temperature (T
A
)
Thermal Resistance (
θ
JA
)
0 to 20 ns/V
0 to 10 ns/V
0 to 5 ns/V
0V to V
CC
0V to 5.5V
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
−
40
°
C to
+
85
°
C
250
°
C/W
Note 1:
Absolute Maximum Ratings: are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
“Recommended Operating Conditions” table will define the conditions for
actual device operation.
Note 2:
Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Control
Input Voltage
LOW Level Control
Input Voltage
HIGH Level Control
Output Voltage
V
CC
(V)
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
V
OL
LOW Level Control
Output Voltage
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
I
IN
I
OFF
I
CC
Input Leakage Current
Power Off Leakage Current
Quiescent Supply Current
0 to 5.5
0.0
1.65 to 5.5
0.08
0.10
0.15
0.22
0.22
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.65
2.3
3.0
4.5
1.52
2.15
2.8
2.68
4.2
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
±0.1
1.0
1.0
Min
0.75 V
CC
0.25 V
CC
0.3 V
CC
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
0.1
0.1
0.1
0.1
0.24
0.3
0.4
0.55
0.55
±1.0
10
10.0
µA
µA
µA
0
≤
V
IN
≤
5.5V
V
IN
or V
OUT
=
5.5V
V
IN
=
5.5V, GND
V
V
IN
=
V
IH
I
OL
=
4 mA
I
OL
=
8 mA
I
OL
=
16 mA
I
OL
=
24 mA
I
OL
=
32 mA
I
OL
=
100
µA
V
V
IN
=
V
IH
I
OH
= −4
mA
I
OH
= −8
mA
I
OH
= −16
mA
I
OH
= −24
mA
I
OH
= −32
mA
I
OH
= −100 µA
1.65 to 1.95 0.75 V
CC
T
A
= +25°C
Typ
Max
T
A
= −40°C
to
+85°C
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
Max
Units
V
V
Conditions
3
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NC7SZ74
AC Electrical Characteristics
Symbol
f
MAX
Parameter
Maximum Clock
Frequency
V
CC
(V)
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
CK to Q, Q
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
PLH
t
PHL
Propagation Delay
CLR, PR, to Q, Q
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
S
Setup Time,
CK to D
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
H
Hold Time,
CK to D
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
W
Pulse Width,
CK, PR, CLR
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
t
REC
Recover Time
CLR, PR to CK
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
3.3
±
0.3
5.0
±
0.5
T
A
= +25°C
Min
75
150
200
250
175
200
2.5
1.5
1.0
0.8
1.0
1.0
2.5
1.5
1.0
0.8
1.0
1.0
6.5
3.5
2.0
1.5
2.0
1.5
0.5
0.5
0.5
0.5
0.5
0.5
6.0
4.0
3.0
2.0
3.0
2.0
8.0
4.5
3.0
3.0
3.0
3.0
6.5
3.8
2.8
2.2
3.4
2.6
6.5
3.8
2.8
2.2
3.4
2.6
12.5
7.5
6.5
4.5
7.0
5.0
14.0
9.0
6.5
5.0
7.0
5.0
Typ
Max
T
A
= −40°C
to
+85°C
Min
75
150
200
250
175
200
2.5
1.5
1.0
0.8
1.0
1.0
2.5
1.5
1.0
0.8
1.0
1.0
6.5
3.5
2.0
1.5
2.0
1.5
0.5
0.5
0.5
0.5
0.5
0.5
6.0
4.0
3.0
2.0
3.0
2.0
8.0
4.5
3.0
3.0
3.0
3.0
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 4
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
CL
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 5
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 4
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 4
13.0
8.0
7.0
5.0
7.5
5.5
14.5
9.5
7.0
5.5
7.5
5.5
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 3
ns
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500
Ω,
S
1
=
Open
Figures
1, 3
MHz
C
L
=
15 pF
R
D
=
1 MΩ
S
1
=
Open
C
L
=
50 pF
R
D
=
500Ω, S
1
=
Open
Figures
1, 5
Max
Units
Conditions
Figure
Number
Capacitance
(Note 3)
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance (Note 4)
Parameter
Typ
3
4
10
12
Note 3:
T
A
= +25C,
f
=
1MHz.
Note 4:
C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
CCD
) at no output
loading and operating at 50% duty cycle. (See Figure 2) C
PD
is related to I
CCD
dynamic operating current by the expression:
I
CCD
=
(C
PD
) (V
CC
) (f
IN
)
+
(I
CC
static).
Max
Units
pF
pF
pF
V
CC
=
0V
V
CC
=
0V
V
CC
=
3.3V
V
CC
=
5.0V
Conditions
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