Standard Products
UT64BS1X433 Matrix-A™ 64-Channel 1:4 Bus Switch
Preliminary Data Sheet
November 12, 2014
www.aeroflex.com/busswitch
FEATURES
Interfaces to standard processor memory busses
Single-chip interface to industry-standard asynchronous
SRAM and PROM memory devices
Eliminates need for additional logic or FPGA
I/O channels functional to 3.3V
R
ON
5 Ohms typical
Flat R
ON
characteristics over channel voltage
Propagation delay 187ps through switch
Transmission gate technology allows for true bi-directional
operation
Bus holders maintain output states on all 64 channels when
de-selected
Logic power 1mW/MHz
Independent 5-bit address decoding to select 1 of 32 devices
Temperature range -55°C to 125°C
Operational environment:
- Intrinsic total-dose: up to 300 krad(Si)
- SEL Immune: <100 MeV-cm
2
/mg @ 125°C
Packaging options:
- 400-pin Ceramic Land Grid, Column Grid and Ball
Grid Array packages; 1mm pitch
Standard Microcircuit Drawing 5962-TBD
- QML Q and V (pending)
APPLICATIONS
- Microprocessor interfaces that require large amounts of
memory
- High-speed applications or systems with large bus
capacitance
- Cost-sensitive applications that require bus isolation
without an expensive FPGA
INTRODUCTION
The UT64BS1X433 Matrix-A™ is a 64-Channel, 1:4 Bus
Switch, that provides bus isolation for up to four banks of 64
I/O connections. By providing bus isolation, the UT64BS1X433
can significantly reduce the amount of load capacitance seen by
a host processor and memory devices. The reduction in both
load capacitance and delay time significantly increase speed and
performance compared with a discrete logic or FPGA memory
interface solution.
The UT64BS1X433 operates from a single 3.3V supply. The
bus channels can pass any voltage between V
SS
and V
DD
,
allowing the switching of signals using other standards, such as
LVCMOS 1.8V.
The UT64BS1X433 has two modes of operation. In mode 0, the
device uses five address and one chip select line to electrically
connect the input bank to one of four output banks and generate
1 of 32 chip select outputs. In mode 1, the device uses eight
address and two chip select lines to independently control two
pairs of two banks with each bank pair controlled by one of the
two chip selects. Mode 1 allows the device to interface two
different types of memory having different address bus
configurations e.g. two PROM banks and two SRAM banks.
The input and output banks connect via analog channels that
have an R
ON
that is nominally 5 Ohms over the entire input
voltage range. The flat R
ON
eliminates the need to add external
series resistors for source impedance termination.
The UT64BS1X433 also provides logic to control up to eight
discrete devices per bank by providing eight individual chip
selects that are decoded using address lines ASEL[2:0] and
BSEL[2:0]. In a fully utilized configuration, the UT64BS1X433
can select up to 32 discrete devices and provide bus isolation to
each bank of eight devices. This makes the device ideally suited
for use with mutli-chip module memory devices, such as the
Aeroflex UT8R1/2/4M39 40/80/160Mbit family of SRAM
devices. Each UT64BS1X433 can interface up to four of the
Aeroflex 160Mb SRAM MCM devices with any Aeroflex
LEON processor without the need for additional logic.
1
36-00-03-001
Aeroflex Microelectronics Solutions - HiRel
INTRODUCTION
The UT64BS1X433 64-Channel 1:4 Bus Switch is built on a 0.35μm Triple-Well CMOS process. The device incorporates control
logic that electrically connects input bank A to the output banks B0-B3, depending upon the selected channel. The control logic also
decodes the address pins to provide chip-select outputs to up to 32 discrete memory devices. To ensure that important memory con-
trol lines e.g. RD and WR are consistently driven, regardless of the switching logic, the Matrix-A provides two 2-to-4 fanout buf-
fers. Typical applications will connect the processor or memory controller’s RD and WR output signals to XIN and YIN on the
Matrix-A, and tie the corresponding XOUTn and YOUTn to the RD and WR memory inputs on each bank.
0A
S
S
S
S
0B0
0B1
0B2
0B3
63A
…
S
S
S
S
63B0
63B1
63B2
63B3
Channel Select
MODE
RAMS
ROMS
ASEL[2:0]
BSEL[2:0]
BANK[1:0]
Decoder Logic
XIN[0]
XIN[1]
XOUT0
XOUT1
XOUT2
XOUT3
YOUT0
YOUT1
YOUT2
YOUT3
CS3[7:0]
CS2[7:0]
CS1[7:0]
CS0[7:0]
YIN[0]
YIN[1]
Figure 1. UT64BS1X433 Functional Block Diagram
2
36-00-03-001
Aeroflex Microelectronics Solutions - HiRel
PIN IDENTIFICATION and DESCRIPTION
Logic Pins
Pin
Number
M11
Pin Name
MODE
Direction
I
Description
Mode select
0: Banks 0-3 are selected with BANK[1:0] and bank 0-3 chip selects are selected
with ASEL[2:0].
1: Banks 0-1 are selected with BANK[0] and bank 0-1 chip selects are selected
with BSEL[2:0]. Banks 2-3 are selected with BANK[1] and bank 2-3 chip
selects are selected with ASEL[2:0].
Enables banks 0-3 in mode 0 and banks 2-3 in mode 1.
Enables banks 0-1 in mode 1. Don’t care in mode 0.
Bit 0 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.
Bit 1 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.
Bit 2 to select chip selects for banks 0-3 in mode 0 and for banks 2-3 in mode 1.
Bit 0 to select chip selects for banks 0-1 in mode 1.
Bit 1 to select chip selects for banks 0-1 in mode 1.
Bit 2 to select chip selects for banks 0-1 in mode 1.
Bit 0 to select banks 0-3 in mode 0 and banks 0-1 in mode 1.
Bit 1 to select banks 0-3 in mode 0 and banks 2-3 in mode 1.
Bank 0 chip select 0. Asserted when xSEL[2:0] = 000b.
Bank 0 chip select 1. Asserted when xSEL[2:0] = 001b.
Bank 0 chip select 2. Asserted when xSEL[2:0] = 010b.
Bank 0 chip select 3. Asserted when xSEL[2:0] = 011b.
Bank 0 chip select 4. Asserted when xSEL[2:0] = 100b.
Bank 0 chip select 5. Asserted when xSEL[2:0] = 101b.
Bank 0 chip select 6. Asserted when xSEL[2:0] = 110b.
Bank 0 chip select 7. Asserted when xSEL[2:0] = 111b.
Bank 0 chip select 0. Asserted when xSEL[2:0] = 000b.
Bank 1 chip select 1. Asserted when xSEL[2:0] = 001b.
Bank 1 chip select 2. Asserted when xSEL[2:0] = 010b.
Bank 1 chip select 3. Asserted when xSEL[2:0] = 011b.
Bank 1 chip select 4. Asserted when xSEL[2:0] = 100b.
Bank 1 chip select 5. Asserted when xSEL[2:0] = 101b.
RAMS
ROMS
ASEL[0]
ASEL[1]
ASEL[2]
BSEL[0]
BSEL[1]
BSEL[2]
BANK[0]
BANK[1]
CS0[0]
CS0[1]
CS0[2]
CS0[3]
CS0[4]
CS0[5]
CS0[6]
CS0[7]
CS1[0]
CS1[1]
CS1[2]
CS1[3]
CS1[4]
CS1[5]
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
M10
N10
P9
P10
R10
U7
N9
M9
U6
U8
W5
Y6
V9
Y4
W9
P8
R9
U10
W6
V7
W8
W4
Y10
R7
5
36-00-03-001
Aeroflex Microelectronics Solutions - HiRel
京公网安备 11010802033920号
EEWORLD
