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MC74VHCT259A
8−Bit Addressable
Latch/1−of−8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the signal on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the VHCT259 as an addressable
latch, changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be done while in
the memory mode.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5.0 V CMOS level output swings.
The VHCT259A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V
CC
= 0 V. These
input and output structures help prevent device destruction caused by
supply voltage−input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
1
VHCT259AG
AWLYWW
16
TSSOP−16
DT SUFFIX
CASE 948F
1
1
VHCT
259A
ALYWG
G
16
SOEIAJ−16
M SUFFIX
CASE 966
1
1
74VHCT259
ALYWG
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
High Speed: t
PD
= 7.6 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs and Outputs
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
January, 2006 − Rev. 4
Publication Order Number:
MC74VHCT259A/D
MC74VHCT259A
1
2
3
13
4
5
6
7
9
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
ADDRESS
INPUTS
A0
A1
A2
A0
A1
A2
Q0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RESET
ENABLE
DATA IN
Q7
Q6
Q5
Q4
DATA IN
RESET
ENABLE
15
14
PIN 16 = V
CC
PIN 8 = GND
Figure 2. Pin Assignment
Figure 1. Logic Diagram
A0
A1
A2
1
2
3
BIN/OCT
1
2
4
0
1
2
3
4
ID
EN
R
5
6
7
4
5
6
7
8
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
1
2
3
DMUX
0
2
0
G
7
0
1
2
3
4
ID
EN
R
5
6
7
4
5
6
7
8
10
11
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
13
14
15
13
14
15
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE
Enable
L
H
L
H
LATCH SELECTION TABLE
Address Inputs
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Reset
H
H
L
L
Mode
Addressable Latch
Memory
8−Line Demultiplexer
Reset
Latch
Addressed
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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2
MC74VHCT259A
DATA INPUT
13
D
4
Q0
D
5
Q1
D
6
Q2
D
A0
ADDRESS
INPUTS
3 TO 8
DECODER
D
A2
7
Q3
A1
9
Q4
D
ENABLE
14
10
Q5
D
11
Q6
D
12
Q7
RESET
15
Figure 4. Expanded Logic Diagram
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3
MC74VHCT259A
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
STG
V
ESD
Positive DC Supply Voltage
Digital Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature Range
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 125°C (Note 4)
SOIC Package
TSSOP
SOIC Package
TSSOP
Output in 3−State
High or Low State
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to V
CC
+0.5
−20
$20
$25
$75
200
180
−65 to +150
>2000
>200
>2000
$300
143
164
Unit
V
V
V
mA
mA
mA
mA
mW
°C
V
I
LATCHUP
q
JA
Latchup Performance
mA
°C/W
Thermal Resistance, Junction−to−Ambient
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range, all Package Types
Input Rise or Fall Time
V
CC
= 5.0 V + 0.5 V
Output in 3−State
High or Low State
Characteristics
Min
4.5
0
0
0
−55
0
Max
5.5
5.5
5.5
V
CC
125
20
Unit
V
V
V
°C
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO
0.1% BOND FAILURES
NORMALIZED FAILURE RATE
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 130
°
C
TJ = 120
°
C
TJ = 110
°
C
TJ = 100
°
C
TJ = 80
°
C
100
TIME, YEARS
TJ = 90
°
C
1
1
10
1000
Figure 5. Failure Rate vs. Time Junction Temperature
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