PSD412A2-12UI datasheet, PDF - EEWORLD Datasheet

PSD412A2-12UI: DescriptionParallel I/O Port, 40 I/O, CMOS, PQFP80,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，97 Pages; ManufacturerWaferscale Integration Inc.

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PSD412A2-12UI Overview

Parallel I/O Port, 40 I/O, CMOS, PQFP80,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Waferscale Integration Inc.
Reach Compliance Code	unknown
Maximum access time	1.2e-7 ns
Other features	GENERAL PURPOSE ZPLD
maximum clock frequency	35.71 MHz
External data bus width	8
JESD-30 code	S-PQFP-G80
JESD-609 code	e0
Number of I/O lines	40
Number of ports	5
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP80,.64SQ
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
ROM size (bits)	512 Bits
Maximum standby current	0.00002 A
Maximum slew rate	40 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
UV erasable	N
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

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