GS81302D08GE-333T datasheet, PDF

Datasheet> All Categories > storage> storage> GS81302D08GE-333T

GS81302D08GE-333T: DescriptionDDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size475KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS81302D08GE-333T Overview

DDR SRAM, 16MX8, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS81302D08GE-333T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	134217728 bit
Memory IC Type	DDR SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

Preview

Download Datasheet

View All

GS81302D08/09/18/36E-375/350/333/300/250

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 144 Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaQuad

-II

Burst of 4 SRAM

Clocking and Addressing Schemes

375 MHz–250 MHz

1.8 V V

1.8 V and 1.5 V I/O

The GS81302D08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Each internal read and write operation in a SigmaQuad-II B4

RAM is four times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore the address

field of a SigmaQuad-II B4 RAM is always two address pins

less than the advertised index depth (e.g., the 16M x 8 has a

4M addressable index).

SigmaQuad™ Family Overview

The GS81302D08/09/18/36E are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302D08/09/18/36E SigmaQuad SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Parameter Synopsis

-375

tKHKH

tKHQV

2.66 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

Rev: 1.04b 12/2011

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

Use CD4011 and CD4017 to make a touch-type five-speed dimmer

μPC1310V power amplifier circuit diagram

Low Cost Voltage Doubler circuit

SC41342 (general) infrared, ultrasonic or radio frequency remote control transmission encoding circuit

Photophotometer circuit

Computer motherboard circuit diagram 810 4_20

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components