AS4C128M16D3LC-12BAN
128M x 16 bit DDR3L Synchronous DRAM (SDRAM)
Features
Standard Compliant
AEC-Q100 Compliant
Power supplies: V
DD
& V
DDQ
=
+1.35V (1.283V ~ 1.45V)
Backward compatible to V
DD
& V
DDQ
=
+1.5V ±0.075V
Operating temperature: T
C
= -40~105°C (Automotive)
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
internal banks for concurrent operation
8n-bit prefetch architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Additive Latency (AL): 0, CL-1, CL-2
Programmable Burst lengths: 4, 8
Burst type: Sequential / Interleave
Output Driver Impedance Control
Average refresh period
8
JEDEC
Advance (Rev. 1.0, Jun. /2019)
Overview
The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank
devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1600 Mb/sec/pin
for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling). All I/Os
are synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.35V -0.067V /
+0.1V power supply.
- DQS & DQS#
Leveling
ZQ Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
Package: Pb and Halogen Free
Write
- 8192 cycles/64ms (7.8us at -40°C
≦
T
C
≦
+85°C)
- 8192 cycles/32ms (3.9us at +85°C
≦
T
C
≦
+95°C)
- 8192 cycles/16ms (1.95us at +95°C
≦
T
C
≦
+105°C)
- Not support self refresh function with T
C
> 95°C
- 96-ball 7.5 x 13 x 1.0mm FBGA
Table 1. Ordering Information
Product part No
Org
Temperature
Max Clock (MHz)
800
Package
96-ball
FBGA
AS4C128M16D3LC-12BAN
128M
x
16
Automotive -40°C to 105°C
Table 2. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
Confidential
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Rev.1.0 June 2019
AS4C128M16D3LC-12BAN
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail
Figure 3. State Diagram
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
Self
Refresh
from any
RESET
state
ZQCL
MRS
ZQ
Calibration
ZQCL,ZQCS
Idle
S
SR RE
X
REF
Refreshing
E
PD DX
P
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Active
Power
Down
PD
PD X
E
Activating
Precharge
Power
Down
Bank
Activating
T
RI
E
A
RE
WR
WRITE
Writing
W
ITE
AD
WRITE
READ
RE
AD
A
READ
Reading
WRITE A
W
E
RIT
A
RE
AD
A
READ A
PRE, PREA
P
E,
PR
RE
,P
Writing
Reading
PR
EA
RE
A
Automatic Sequence
Command Sequence
Precharging
Confidential
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Rev.1.0 June 2019
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