128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
FLASH AND CellularRAM
™
COMBO MEMORY
Features
Stacked die Combo package
• Includes two 64Mb Flash devices
• Choice of either one 32Mb or one 64Mb CellularRAM
device
Basic configuration
Flash
• Flexible multibank architecture
• 4 Meg x 16 configuration
• Async/Page/Burst interface
• Support for true concurrent operations with no latency
CellularRAM
• Low-power, high-density design
• 2 Meg x 16 or 4 Meg x 16 configurations
• Burst interface
F_V
CC
, V
CC
Q, F_V
PP
, C_V
CC
voltages
• 1.70V (MIN)/1.95V (MAX) F_V
CC
, C_V
CC
• 1.70V (MIN)/2.24V (MAX) V
CC
Q (W18)
• 2.20V (MIN)/3.30V (MAX) V
CC
Q (W30)
• 1.80V (TYP) F_V
PP
(in-system PROGRAM/ERASE)
•
12V ±5% (HV) F_
V
PP
tolerant (factory programming
MT28C128532W18/W30E
MT28C128564W18/W30E
Low Voltage, Wireless Temperature
Figure 1: 77-Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
A4
2
A18
3
A19
4
C_VSS
5
F_VCC
6
F_VCC
7
A21
8
A11
A5
C_LB#
C_VSS
NC
CLK
RFU
A12
A3
A17
F_VPP
C_WE#
C_CE#
A9
A13
A2
A7
F_WP#
ADV#
A20
A10
A15
A1
A6
C_UB#
F_RST#
F_WE#
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT#
F_CE2#
C_OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F_OE2#
NC
F_OE1#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
F_CE1#
NC
NC
NC
C_VCC
F_VCC
VCCQ
C_CRE
compatibility)
Fast programming Algorithm (FPA)
Enhanced suspend options
• ERASE-SUSPEND-to-READ within same bank
• PROGRAM-SUSPEND-to-READ within same bank
• ERASE-SUSPEND-to-PROGRAM within same bank
Each Flash contains two 64-bit chip protection registers for
security purposes
100,000 ERASE cycles per block
Cross-compatible command set support
• Extended command set
• Common Flash interface (CFI) compliant
Manufacturer’s Identification Code (ManID)
• Micron
®
• Intel
®
C_VSS
VSSQ
VCCQ
F_VCC
C_VSS
VSSQ
F_VSS
C_VSS
Top View
(Ball Down)
Options
Flash Timing
• 60ns
1
(W18)
• 70ns (W18/W30)
Flash Burst Frequency
• 66 MHz
1
(W18)
• 54 MHz (W18/W30)
Flash Boot Block Configuration
• Top/Top
• Top/Bottom
• Bottom/Top
• Bottom/Bottom
CellularRAM Timing
• 70ns
• 85ns
CellularRAM Burst Frequency
• 66 MHz
I/O Voltage Range
• VccQ 1.70V–2.24V (W18)
• VccQ 2.20V–3.30V (W30)
Manufacturer’s Identification Code (ManID)
• Micron (0x2Ch)
• Intel (0x89h)
Operating Temperature Range
• Wireless Temperature (-25°C to +85°C)
Package
• 77-ball FBGA (Standard) 8 x 10 grid
• 77-ball FBGA (Lead-free) 8 x 10 grid
2
NOTE:
1. Contact factory for availability.
2. Contact factory for details.
09005aef80df9a45
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Device General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Flash General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Flash Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
CellularRAM General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Part Number Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Boot Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
MultiChip Packaging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Unique IDs, State Machines, and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Flash Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
09005aef80df9a45
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
77-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
09005aef80df9a45
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Possible Boot Configurations for Flash Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
09005aef80df9a45
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
128Mb MULTIBANK BURST FLASH
32Mb/64Mb BURST CellularRAM COMBO
Device General Description
The MT28C128532W18/W30E/MT28C128564W18/
W30E combination Flash and CellularRAM devices are
a high-performance, high-density, memory solution
that can significantly improve system performance.
This memory solution is comprised of two 64Mb Flash
devices and one 32Mb or one 64Mb CellularRAM
device.
It is important to note that the specifications con-
tained in this document supersede the specifications
listed in the referenced individual Flash and Cellular-
RAM data sheets.
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top).
CellularRAM General Description
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed
for low-power portable applications The CellularRAM
device is available in either 32Mb or 64Mb densities.
Two user-accessible control registers define the
device operation. The bus configuration register (BCR)
defines how the CellularRAM device interacts with the
system memory bus and is nearly identical to its
counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how
refresh is performed on the CellularRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated anytime during
normal operation.
To operate seamlessly on a burst Flash bus,
CellularRAM
products
have
incorporated
a
transparent self-refresh mechanism. The hidden
refresh requires no additional support from the system
memory controller and has no significant impact on
device read/write performance.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
sleep mode halts the refresh operation altogether and
is used when no vital information is stored in the
device. These three refresh mechanisms are adjusted
through the refresh configuration register (RCR).
For device specifications and additional documen-
tation concerning CellularRAM features, please refer to
the
MT45W2MW16BFB,
MT45W2ML16BFB,
MT45M4MW16BFB, and MT45W4ML16BFB data
sheets at
www.micron.com/cellularram.
Flash General Description
The Flash architecture features a multipartition
configuration that supports READ-While-PROGRAM/
ERASE operations with no latency. A 4Mb partition size
enables optimal design flexibility.
Two Flash devices are stacked to achieve the 128Mb
density. Each Flash die has a dedicated CE# and OE#
control.
The stacked Flash device enables soft protection for
blocks, as read only, by configuring soft protection reg-
isters with dedicated command sequences. For secu-
rity purposes, two user-programmable 64-bit chip
protection registers are provided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the
memory bus. For device specifications and additional
documentation concerning Flash features, please refer
to the MT28F644W18 data sheet at
www.micron.com/
flash.
Flash Configurations
Each Flash memory implements a multibank archi-
tecture (16 banks of 4Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.
Each Flash memory features eight 4K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 32K
09005aef80df9a45
MT28C128564W18E.fm - Rev. C Pub 2/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
京公网安备 11010802033920号
EEWORLD
