CD4503B Types
COs/MOS Hex Buffer
Features:
High-Voltage Types (20-Volt Rating)
3-State Non-Inverting Type
DISAfLE
..!I+===~
3 01
The RCA-C045038 is a hex noninverting
buffer with 3-state outputs having high sink-
and source-current capability. Two disable
controls are provided, one of which controls
four buffers and the other controls the
remaining two buffers. The C045038 types
are supplied in l6-lead hermetic dual-In-
line ceramic packages (0 and F suffixes),
l6-lead dual-i n-line plastic packages (E suf-
fix), l6-lead ceramic flat packages (K SUffiX),
and in chip form (H suffix).
1 TTL-Ioad output drive capability
2 output·dlsable controls
3-state outputs
Pin compatible with Industry types MM80C97,
MC14S03, and 340097
• S-V, 10-V, and 15-V parametric ratings
• Maximum Input current of 1/AA at 18 V over full
0
package·temperature range; 100 nA at 18 V and 25 C
• Meets all requirements of JEDEC
Tentative Standard No. 13A, "Standard
Specifications for Description of 'B'
Series CMOS Devices"
•
•
•
•
DI
02
03
04
10
06
14
13
Q6
DIS,\BLE.:..:I~t:=====....J
le-voo a-vss
Applications:
• 3·state hex buffer for Interfacing IC's
with data buses
• COS/MOS to TTL hex buffer
FUNCTIONAL DIAGRAM
D*
N
2 14,6,10,12,14)
,..-----t-t
TRUTH TABLE
ON
DIS AlB)
ON
0
I
X
0
0
I
0
I
HIGH Z
3
4
~
6
x·
DRAIN·TO·SOURCE IoOI.TAGE (I!o!i-V ..c .... " .
DON'T CARE
Fig.
2-
Typical n·channel output low (sink)
current characteristics.
*ALL INPUTS PROTECTED
BY COSIMOS PROTECTION
NETWORK
92CM'323U
Fig. 1-Logic diagram of
1
to
6
identical buffers
-TO-SOURCE VOLTAGE IVDSI-V
,2(1"3273'
MAXIMUM RATINGS,
Absolute·Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDD)
(Voltages referenced to VSS Terminal) .... ..... .
INPUT VOLTAGE RANGE, ALL INPUTS.
DC INPUT CURRENT, ANY ONE INPUT ....... .
POWER DISSIPATION PER PACKAGE (PO)
For T A
=
-40 to + 600C (PACKAGE TYPE E) .. .
Derate Linearly
For TA
=
+ 60 to + 85'C (PACKAGE TYPE E). ..
-55 to + 100'C (PACKAGE TYPES 0, F) ... .
For TA
For TA
=
+ 100 to + 125'C (PACKAGE TYPES 0, F) ...... . Derate Linearly
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA
FULL PACKAGE·TERMPERATURE RANGE (All Package Types)
OPERA TlNG·TEMPERATURE RANGE
(T
A)·
PACKAGE TYPES 0, F, H . . . .. .
PACKAGE TYPE E ..... .
STORAGE TEMPERATURE RANGE
(T
stg) ...... .
LEAD TEMPERATURE (DURING SOLDERING)
At distance
1/16
±
1/32
inch (1 59 ± 0.79 mm) from case for 10 s max
. -0 5to +20V
-05toVDD +05V
.. ±10mA
Fig. 3-Minimum n·channel output low (sink)
current characteristics.
DIS A
16
15
14
13
12
10
Voo
DIS B
=
=
.500mW
at 12
mW/'C
to 200 mW
. .......... 500mW
at 12
mW/'C
to 200 mW
100mW
-55to
+
125'C
. ...... -40 to
+
85'C
-65to
+
l50'C
01
01
02
02
03
03
VSS
06
06
05
05
D4
04
T
VI W
uCI-azall
TERMINAL ASSIGNMENT
.. +
265'C
290 ________________________________________________________________________
CD4503B Types
STATIC EI.ECTRICAL
C~ARACTERISTICS
CHARJ~C·
DRAIN·TO-SOURC% YOLTAGE lYDS'-V
·9·8·7·8
-10
CONDITIONS
TERlsrlC
LIMITS AT INDU:JlITED TEMPERATURES ('C)
Values et -55,
+
2!;,
+
125 Apply to D,F,H Packages
Valuas
at
-4O,.~ ~:5,
+
85 Apply to E Package
U
N
I
Vo
(V)
T
V(V)IN
V(V)DD
-55
-40
+
85
+
125 Min.
::'5
•
7""
_,.......
II ...
S
~:~:ntl-----~~~,'15~0-~~+-~21-+_~~4-:~-.+-:~4-_--~~~:~~~-~~
Current,
100 Max.
0,15
0,20
0.4
0.5
1.5
15
20
4
20
2.6
6.5
19.2
4
20
2.5
6.4
18.9
120
120
~
-
_600
1.4
3.9
11.4
0.02
0.04
2.3
6.2
23
4
20
OutPUt
Low
(Sink)
Current
IOl Min.
I
o
o
o
5
10
15
1.3
3.8
11.2
2.1
5.5
16.1
-
mA
Fig.
4-
Typical p-channel output high (source)
current characteristics
l
O~~;~t
1-
_~
41.~6~5-+_~5~.1~
.21-_·.:.::-1.1~61
--:.0:.:.:..7.+_ ..::..:0.
=--+-7f-....!..1.~m-_·~
1.9~
____
-
(Source)
_~
.
5+-5~~5.,......-+~
2!~
-5;~.8----..;;,-5
......-+-71
-_.3~.;.4=+-~·3:-f1---=
.
8_·~6
::-t-1____
.
-4-=+- .
-
Current. '--=1,9
~.:.::....5.:+-..:..:1t0:---f-_1..:..:10~----=.:3.~
__
1
·3-+_. 1.
.:..:..9+_-·~
....;
11.~81--.;;.
-2.~6---=.:31
.
~7_-~
IOH Min.
I~.'"
15
15 -8.2
·8
-4.9
·4.8 1-6.81-14.1
Output
0.05
Voltan e :
5
0.5
o
0.05
Low·
Level.
o
0.05
0.10
10
0.05
0.15
15
VOL
Max.
o
Output
4.95
5
4.95
5
Voltaoe:
0.5
High·
Level.
0.10
10
9.95
10
.9.95
i
VOH Min.
0.15
15
14.95
,14.95 15
, Input Low 0.5.4.5
5
1.5
1.5
P
Voltan • "':"';';'1":""""':
.94---+--:"'-
1
O-l-----...,,3~·-----+-_-+-_--+--=3---t
e
VIL Max. 1.5.13.5
15
4
4
i'lnput
High
0.5.4.5
-
5
3.5
3.5
Voltaoe.
1.9
10
7
7
VIH Min."'" •
·1.~13-=+-.5--+-..,..,,115:-+----..,.-:111-·-----+-..,.-:111-+---+----1
11.5",....:
V
-
Fig. 5-Mlnlmum p-channel output high (source)
current characteristics.
I
V
Input
Current
liN Max.
3·State
OutPUIt
Leakage
0,18
Current,
lOUT
Max.
I
0,18
18
±0.1
±0.1
±1
±1
± 10.5 ±0.1
0.18
18
±0.4
±0.4
±12
±12
LOAD CAPACITANCE lCL l-pF
FIg.
6-
Typical propagation delay time
as a
function of load capacitance.
REC()MMENDED OPERATING CONDITIONS
F r maximum reliability, nominal operating c:andltions should be selected so
that operatl n Is always within the following ranges:
.--'
CttARACTERISTIC
f--.
LIMI
Min.
T·~S--------~------~
Max.
18
UNITS
Supply,VI)ltage Range (For
TA
=
Full Package·
Temperature Range)
3
v
Fig.
7-
TYPIcal transition time
as a
function
of load capacitance.
291
CD4503B Types
DYNAMIC ELECTRICAL CHARACTERISTICS at TA
25°C; Input t
r •
tf
CL
=
50 pF. RL
200 kQ unless otherwise specified.
=
=
20n8.
INPUTS
CHARACTERISTIC
Voo
(V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
LIMITS
Typ.
Max.
UNITS
Vss
o
Propagation Delay Time:
Low·to·Hlgh. tplH
Hlgh·to·low. tpHl
Transition Time:
low·to·High. tTlH
High·to·low, tTHl
3·State Propagation Delay Time:
tpHZ' tpZH
tpZl. tpLZ
75
35
25
55
25
17
50
30
25
35
20
13
70
30
25
90
40
35
Voo
150
70
50
110
50
35
90
45
35
70
40
25
140
60
50
180
80
70
ns
ns
9ZCS-Z740IRI
ns
Fig. 10-Quiescent·devlce·current test circuit.
ns
os
INPUTQVOO
OUTPUTS
VIH
ns
V~
'-
VSS
~
~
NOTE:
TEST
ANY
CONBINATIONe
Of'INPUTS
92CS-27441RI
500,.F
16 •
Fig. 1'-lnput·voltage test circuit.
Voo
. . .
1102
1NPUO'
'00
"m
MEASURE INPUTS
SEQUENTIAI.I.Y,
TO 90TH Voo AND Vss
CONN ECT A
1.1.
UNUSED
INPUTS TO EITHER
Voo OR Vss
I
Z
. . . 1
10
2
t
..
•
1
FREQUENCY
It
'-KHz
10
,
t
. . .
ItO"
o
~
Vss
92CS-32141
~
••c ......o
Fig.
8-
Typical power dissipation
as a
function
of frequency
Fig. 9-Dynamic power dissipation test circuit.
Vss
Fig. 12-lnput current test circuit.
Dimensions and pad layout for CD4503BH
D,mens,ons
In
parentheses are
In
mllllmelers and
are de"ved Irom the basIc Inch d,mensIons
In'
d,cated G"d graduations are
In
mtls
ocr
3
Inch/'
as
The photographs and dimensions represent
a chIp when IllS part of Ihe wafer. When Ihe
wafer,: cuI mto
chlp~.
the cleallage angles
are
57
mstead of
90
wIth respect to the
face of the chIp. Therefore, the Isolated
chIp IS actually
7
mtls (0
17
mmJ larger
on
both d,mens,ons
292