EP610SC-15 datasheet, PDF - EEWORLD Datasheet

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EP610SC-15: DescriptionOT PLD, 17ns, PAL-Type, CMOS, PDSO24, PLASTIC, SO-24; CategoryProgrammable logic devices Programmable logic; File Size285KB，42 Pages; ManufacturerAltera (Intel)

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EP610SC-15 Overview

OT PLD, 17ns, PAL-Type, CMOS, PDSO24, PLASTIC, SO-24

EP610SC-15 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	SOIC
package instruction	SOP, SOP24,.4
Contacts	24
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	MACROCELLS INTERCONNECTED BY GLOBAL BUS; 16 MACROCELLS; 2 EXTERNAL CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	71.4 MHz
JESD-30 code	R-PDSO-G24
JESD-609 code	e0
Dedicated input times	4
Number of I/O lines	16
Number of entries	20
Output times	16
Number of product terms	160
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 16 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP24,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	17 ns
Certification status	Not Qualified
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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Classic

EPLD Family

Data Sheet

May 1999, ver. 5

Features

Complete device family with logic densities of 300 to 900 usable gates

(see

Table 1)

Device erasure and reprogramming with non-volatile EPROM

configuration elements

Fast pin-to-pin logic delays as low as 10 ns and counter frequencies

as high as 100 MHz

24 to 68 pins available in dual in-line package (DIP), plastic J-lead

chip carrier (PLCC), pin-grid array (PGA), and small-outline

integrated circuit (SOIC) packages

Programmable security bit for protection of proprietary designs

100% generically tested to provide 100% programming yield

Programmable registers providing D, T, JK, and SR flipflops with

individual clear and clock controls

Software design support featuring the Altera

MAX+PLUS

development system on Windows-based PCs, as well as

Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000

workstations, and third-party development systems

Programming support with Altera’s Master Programming Unit

(MPU); programming hardware from Data I/O, BP Microsystems,

and other third-party programming vendors

Additional design entry and simulation support provided by EDIF,

library of parameterized modules (LPM), Verilog HDL, VHDL, and

other interfaces to popular EDA tools from manufacturers such as

Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,

Synplicity, and VeriBest

Table 1. Classic Device Features

Feature

Usable gates

Macrocells

Maximum user I/O pins

(ns)

CNT

(MHz)

EP610

EP610I

300

100

EP910

EP910I

450

76.9

EP1810

900

Altera Corporation

A-DS-CLASSIC-05

745

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