Features
•
Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
•
•
– V
CC
= 1.7V to 5.5V
Internally Organized 256 x 8 (2K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1MHz (5V), 400kHz (1.7V, 2.5V, 2.7V) Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (2K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Green (Pb/Halide-free/RoHS Compliant) Package Options
Die Sales: Wafer Form and Tape and Reel
•
•
Two-wire
Serial Electrically
Erasable and
Programmable
Read-only Memory
2K (256 x 8)
Description
The Atmel
®
AT24C02C provides 2048-bits of serial electrically erasable and program-
mable read-only memory (EEPROM) organized as 256-words of 8-bits each. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The AT24C02C is available in space-
saving 8-lead PDIP, 8-lead TSSOP, 8-lead JEDEC SOIC, 8-lead UDFN
,
5-lead
SOT23 and 8-ball VFBGA packages and is accessed via a two-wire serial interface.
Table 0-1.
Pin Name
A0 - A2
SDA
SCL
WP
GND
VCC
Note:
Atmel AT24C02C
Pin Configuration
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
Ground
Power Supply
A0
A1
A2
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead UDFN
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
For use of 5-lead
SOT23, the software
A2, A1, and A0 bits in
the device address
word must be set to
zero to properly
communicate
Bottom View
5-lead SOT23
SCL
GND
SDA
1
2
3
4
VCC
5
WP
8-ball VFBGA
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
Bottom View
8700D–SEEPR–8/10
Absolute Maximum Ratings
Operating Temperature ........................–55°C to +125°C
Storage Temperature ...........................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................... –1.0V to +7.0V
Maximum Operating Voltage................................. 6.25V
DC Output Current .............................................. 5.0 mA
*NOTICE:
Stresses beyond those listed under “Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating condi-
tions for extended periods may affect device
reliability.
Figure 0-1.
VCC
GND
WP
SCL
SDA
Block Diagram
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A
2
A
1
A
0
R/W
COMP
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
INC
X DEC
EEPROM
LOAD
DATA WORD
ADDR/COUNTER
Y DEC
SERIAL MUX
D
IN
D
OUT
D
OUT
/ACK
LOGIC
2
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
1.
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1 and A0 pins are device address inputs that are hard wired
for the Atmel
®
AT24C02C. As many as eight 2K devices may be addressed on a single bus system (device
addressing is discussed in detail under the Device Addressing section).
WRITE PROTECT (WP):
AT24C02C has a write protect pin that provides hardware data protection. The write
protect pin allows normal read/write operations when connected to ground (GND). When the write protect pin is
connected to V
CC
, the write protection feature is enabled and operates as shown in
Table 1-1.
Table 1-1.
WP Pin
Status
At V
CC
At GND
Write Protect
Part of the Array Protected
Atmel 24C02C
Full (2K) Array
Normal Read/Write Operations
3
8700D–SEEPR–8/10
2.
Memory Organization
Atmel AT24C02C, 2K SERIAL EEPROM:
Internally organized with 32 pages of 8-bytes each, the 2K requires an
8-bit data word address for random word addressing.
Table 2-1.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25⋅C, f = 1.0MHz, V
CC
= +1.7V to +5.5V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, A
2
, SCL)
1. This parameter is characterized and is not 100% tested
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: T
AI
=
–
40°C to +85°C, V
CC
= +1.7V to +5.5V (unless otherwise noted)
Symbol
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 1.7V
Standby Current V
CC
= 2.5V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.7V
I
OL
= 2.1mA
I
OL
= 0.15mA
READ at 100kHz
WRITE at 100kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
–0.6
V
CC
x 0.7
Test Condition
Min
1.7
2.5
2.7
4.5
0.4
2.0
0.6
1.4
1.6
8.0
0.10
0.05
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
3.0
4.0
4.0
18.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
V
V
mA
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested
4
Atmel AT24C02C
8700D–SEEPR–8/10
Atmel AT24C02C
Table 2-3.
AC Characteristics
Applicable over recommended operating range from T
AI
=
–
40°C to +85°C, V
CC
= +1.7V to +5.5V, CL = 1TTL Gate and
100pF (unless otherwise noted)
1.7, 2.5, 2.7
Symbol
f
SCL
t
LOW
t
HIGH
t
I
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start
Start Hold Time
Start Setup Time
Data In Hold Time
Data In Setup Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Setup Time
Data Out Hold Time
Write Cycle Time
5.0V, 25⋅C, Byte Mode
0.6
50
5
1 Million
0.1
1.2
0.6
0.6
0
100
0.3
300
.25
50
5
1.2
0.6
50
0.9
0.05
0.5
0.25
0.25
0
100
0.3
100
Min
Max
400
0.4
0.4
50
0.55
Min
5.0V
Max
1000
Units
kHz
µs
µs
ns
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is ensured by characterization only
5
8700D–SEEPR–8/10
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