NM93CS06L/CS46L/CS56L/CS66L 256-/1024-/2048-/4096-Bit Serial EEPROM with Extended Voltage
(2.7V to 5.5V) and Data Protect (MICROWIRE Bus Interface)
NM93CS06L/CS46L/CS56L/CS66L
March 1997
NM93CS06L/CS46L/CS56L/CS66L
256-/1024-/2048-/4096-Bit Serial EEPROM
with Extended Voltage (2.7V to 5.5V) and Data Protect
(MICROWIRE
™
Bus Interface)
General Description
The NM93CS06L/CS46L/CS56L/CS66L devices are 256/
1024/2048/4096 bits, respectively, of non-volatile electrically
erasable memory divided into 16/64/128/256 x 16-bit regis-
ters (addresses). The NM93CSxxL Family functions in an
extended voltage operating range, and is fabricated using
Fairchild Semiconductor’s floating gate CMOS technology
for high reliability, high endurance and low power consump-
tion. N registers (N
≤
16, N
≤
64, N
≤
128, N
≤
256) can be
protected against data modification by programming the Pro-
tect Register with the address of the first register to be pro-
tected against data modification. (All registers greater than,
or equal to, the selected address are then protected from fur-
ther change.) Additionally, this address can be “locked” into
the device, making all future attempts to change data impos-
sible.
These devices are available in both SO and TSSOP pack-
ages for small space considerations.
The serial interface that controls these EEPROMs is MI-
CROWIRE compatible, providing simple interfacing to stan-
dard microcontrollers and microprocessors. There are a total
of 10 instructions, 5 which operate on the EEPROM memory
and 5 which operate on the Protect Register. The memory in-
structions are READ, WRITE, WRITE ALL, WRITE EN-
ABLE, and WRITE DISABLE. The Protect register instruc-
tions are PRREAD, PRWRITE, PRCLEAR, PRDISABLE and
PRENABLE.
Features
n
n
n
n
n
n
n
n
n
n
n
n
Sequential register read
Write protection in a user defined section of memory
2.7V to 5.5V operating range in all modes
Typical active current of 200 µA; typical standby current
of 1 µA
No erase required before write
Reliable CMOS floating gate technology
MICROWIRE compatible serial I/O
Self timed write cycle
Device status during programming mode
40 year data retention
Endurance: 10
6
data changes
Packages Available: 8-pin SO, 8-pin DIP, and 8-pin
TSSOP
Block Diagram
DS010044-1
© 1997 Fairchild Semiconductor Corporation
DS010044
www.fairchildsemi.com
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PrintDate=1997/08/06 PrintTime=13:14:07 5601 ds010044 Rev. No. 6
cmserv
Proof
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Connection Diagrams
Dual-In-Line Package (N)
8-Pin SO Package (M8) and
8-Pin TSSOP Package (MT8)
Pin Names
CS
SK
DI
DO
GND
PE
PRE
V
CC
DS010044-2
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Protect Register Enable
Power Supply
Top View
See Package Number N08E (N)
See Package Number M08A (M8)
See Package Number MTC08 (MT8)
Ordering Information
Commercial Temp. Range (0˚C to +70˚C)
Order Number
NM93CS06LN/NM93CS46LN/NM93CS56LN/NM93CS66LN
NM93CS06LM8/NM93CS46LM8/NM93CS56LM8/NM93CS66LM8
NM93CS46LMT8/NM93CS56LMT8/NM93CS66LMT8
Extended Temp. Range (−40˚C to +85˚C)
Order Number
NM93CS06LEN/NM93CS46LEN/NM93CS56LEN/NM93CS66LEN
NM93CS06LEM8/NM93CS46LEM8/NM93CS56LEM8/NM93CS66LEM8
NM93CS46LEMT8/NM93CS56LEMT8/NM93CS66LEMT8
Automotive Temp. Range (−40˚C to +125˚C)
Order Number
NM93CS06LVN/NM93CS46LVN/NM93CS56LVN/NM93CS66LVN
NM93CS06LVM8/NM93CS46LVM8/NM93CS56LVM8/NM93CS66LVM8
NM93CS46LVMT8/NM93CS56LVMT8/NM93CS66LVMT8
www.fairchildsemi.com
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PrintDate=1997/08/06 PrintTime=13:14:08 5601 ds010044 Rev. No. 6 cmserv
Proof
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DC and AC Electrical Characteristics: 4.5V
<
V
CC
<
5.5V
Symbol
t
SKS
t
CS
t
CSS
t
PRES
t
DH
t
PES
t
DIS
t
CSH
t
PEH
t
PREH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
WP
Parameter
SK Setup Time
Minimum CS
Low Time
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in
TRI-STATE
Write Cycle Time
CS = V
IL
Part Number
Conditions
SK must be at V
IL
for
t
SKS
before CS goes High
(Note 2)
(Continued)
Min
50
250
50
50
70
50
100
0
250
50
20
500
500
500
100
10
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Capacitance
Symbol
C
OUT
C
IN
(Note 3)
Test
Max
5
5
Units
pF
pF
T
A
= 25˚C f = 1 MHz
Output Capacitance
Input Capacitance
Note 1:
Stress ratings above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and operation
of the device at these or any other conditions above those indicated in the operational sections of the specification is oonot implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Note 2:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal device registers (device reset) prior to beginning another
opcode cycle (This is shown in the opcode diagrams in the following pages).
Note 3:
This parameter is periodically sampled and not 100% tested.
Note 4:
Typical leakage values are in the 20 nA range.
Note 5:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum SK clock speed (minimum SK period) is determined by the
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not allowable to set
1/f
SK
= t
SKH (minimum)
+ t
SKL (minimum)
for shorter SK cycle time operation,
5
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PrintDate=1997/08/06 PrintTime=13:14:12 5601 ds010044 Rev. No. 6 cmserv
Proof
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