Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5510
Rev. 3, 3/2009
MPC5510
MAPBGA–208
MAPBGA–225
17 mm x 17 mm
15 mm x 15 mm
LQFP–144
QFN12
20 mm x 20
##_mm_x_##mmmm
LQFP–176
24 mm x 24 mm
PKG-TBD
## mm x ## mm
MPC5510 Microcontroller
Family Data Sheet
MPC5510 Family Features
• Single issue, 32-bit CPU core complex (e200z1)
– Compliant with the Power Architecture™ embedded
category
– Includes an instruction set enhancement allowing
variable length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed 16-bit
and 32-bit instructions, it is possible to achieve
significant code size footprint reduction.
• Up to 1.5-Mbyte on-chip flash with flash control unit
(FCU)
• Up to 80 Kbytes on-chip SRAM
• Memory protection unit (MPU) with up to sixteen region
descriptors and 32-byte region granularity
• Interrupt controller (INTC) capable of handling
selectable-priority interrupt sources
• Frequency modulated Phase-locked loop (FMPLL)
• Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
• 16-channel enhanced direct memory access controller
(eDMA)
• Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
• Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS200)
• Up to 40-channel 12-bit analog-to-digital converter (ADC)
• Up to four serial peripheral interface (DSPI) modules
• Media Local Bus (MLB) emulation logic (works with two
DSPIs, the e200z0, the eDMA, and system RAM to create
a 3-pin or 5-pin 256Fs MLB protocol)
• Up to eight serial communication interface (eSCI) modules
• Up to six enhanced full CAN (FlexCAN) modules with
configurable buffers
• One inter IC communication interface (I
2
C) module
SOT-343R
##_mm_x_##mm
TBD
• Up to 144 configurable general purpose pins supporting
input and output operations and 3.0V through 5.5V supply
levels
• Real-time counter (RTC_API) with clock source from
external 32-kHz crystal oscillator, internal 32-kHz or
16-MHz oscillator and supporting wake-up with selectable
1-second resolution and > 1-hour timeout, or 1-millisecond
resolution with maximum timeout of one second
• Up to eight periodic interrupt timers (PIT) with 32-bit
counter resolution
• Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
• Device/board test support per Joint Test Action Group
(JTAG) of IEEE (IEEE 1149.1)
• On-chip voltage regulator (VREG) for regulation of 5V
input to 1.5V and 3.3V internal supply levels
• Optional e200z0, second Power Architecture based I/O
processor with VLE instruction set
• Optional FlexRAY controller
• Optional external bus interface (EBI) module
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
Table of Contents
1
Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4
1.1 Signal Properties and Multiplexing Summary . . . . . . . . .4
1.2 Power and Ground Supply Summary . . . . . . . . . . . . . .15
1.3 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.4 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5 Pinout – 208 PBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 General Notes for Specifications at Maximum
Junction Temperature . . . . . . . . . . . . . . . . . . . .21
2.3 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.4 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .25
2.5 Operating Current Specifications
. . . . . . . . . . . . . .27
2.6 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .29
2.7 Low Voltage Characteristics . . . . . . . . . . . . . . . . . . . . .30
2.8 Oscillators Electrical Characteristics. . . . . . . . . . . . . . .31
2.9 FMPLL Electrical Characteristics . . . . . . . . . . . . . . . . .33
2.10 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . .34
2.11 Flash Memory Electrical Characteristics. . . . . . . . . . . .35
2.12 Pad AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . .36
2.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.13.1 Reset and Boot Configuration Pins . . . . . . . . . .37
2.13.2 External Interrupt (IRQ) and Non-Maskable
Interrupt (NMI) Pins . . . . . . . . . . . . . . . . . . . . .37
2.13.3 JTAG (IEEE 1149.1) Interface . . . . . . . . . . . . . .38
2.13.4 Nexus Debug Interface . . . . . . . . . . . . . . . . . . .41
2.13.5 External Bus Interface (EBI) . . . . . . . . . . . . . . .43
2.13.6 Enhanced Modular I/O Subsystem (eMIOS) . . .46
2.13.7 Deserial Serial Peripheral Interface (DSPI) . . . .47
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 13. 5V Low Frequency (32 kHz) Internal RC Oscillator . . . 32
Table 14. FMPLL Electrical Specifications . . . . . . . . . . . . . . . . . 33
Table 15. eQADC Conversion Specifications (Operating) . . . . . . 34
Table 16. Flash Program and Erase Specifications . . . . . . . . . . . 35
Table 17. Flash EEPROM Module Life (Full Temperature Range) 35
Table 18. Pad AC Specifications (VDDE = 3.0V - 5.5V) . . . . . . . 36
Table 19. Reset and Boot Configuration Timing . . . . . . . . . . . . . 37
Table 20. IRQ/NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 22. Nexus Debug Port Timing . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. External Bus Operation Timing . . . . . . . . . . . . . . . . . . 43
Table 24. eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Revision History of MPC5510 Data Sheet . . . . . . . . . . 53
2
List of Figures
Figure 1. MPC5510 Family Block Diagram . . . . . . . . . . . . . . . . . . 3
Figure 2. MPC5510 Pinout – 144 LQFP . . . . . . . . . . . . . . . . . . . 17
Figure 3. MPC5510 Pinout – 176 LQFP . . . . . . . . . . . . . . . . . . . 18
Figure 4. MPC5510 Pinout – 208 PBGA . . . . . . . . . . . . . . . . . . . 19
Figure 5. Pad Output Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 6. Reset and Boot Configuration Timing. . . . . . . . . . . . . . 37
Figure 7. IRQ and NMI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. JTAG Test Clock Input Timing. . . . . . . . . . . . . . . . . . . . 38
Figure 9. JTAG Test Access Port Timing . . . . . . . . . . . . . . . . . . . 39
Figure 10. JTAG JCOMP Timing . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. JTAG Boundary Scan Timing . . . . . . . . . . . . . . . . . . . 40
Figure 12. Nexus Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 13. Nexus TDI, TMS, TDO Timing . . . . . . . . . . . . . . . . . . 42
Figure 14. CLKOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 15. Synchronous Output Timing . . . . . . . . . . . . . . . . . . . . 44
Figure 16. Synchronous Input Timing . . . . . . . . . . . . . . . . . . . . . 45
Figure 17. Address Latch Enable (ALE) Timing . . . . . . . . . . . . . 46
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0 . . . . . 48
Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1 . . . . . 48
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0 . . . . . . 49
Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1 . . . . . . 49
Figure 22. DSPI Modified Transfer Format Timing — Master,
CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. DSPI Modified Transfer Format Timing — Master,
CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA = 0
51
Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA = 1
51
Figure 26. DSPI PCS Strobe (PCSS) Timing . . . . . . . . . . . . . . . 51
3
4
List of Tables
Table 1. MPC5510 Signal Properties . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. MPC5510 Power/Ground . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . .20
Table 4. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 5. ESD Ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 6. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . .25
Table 7. Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 8. I/O Pad Average DC Current . . . . . . . . . . . . . . . . . . . . . .29
Table 9. Low Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 10. 3.3V High Frequency External Oscillator. . . . . . . . . . . .31
Table 11. 5V Low Frequency (32 kHz) External Oscillator . . . . . .31
Table 12. 5V High Frequency (16 MHz) Internal RC Oscillator . . .32
MPC5510 Microcontroller Family Data Sheet, Rev. 3
2
Freescale Semiconductor
Oscillators
e200z1 Core
Integer
Execution
Unit
Multiply
Unit
Instruction
Unit
PPC & VLE
General Purpose
Registers
(32 x 32-bit)
Timers
JTAG
Branch
Unit
Load/Store
Unit
FlexRay
Instruction Bus
Data Bus
eDMA
Instruction
Unit
VLE
NDI
FMPLL
VREG
MPC5510
INTC
e200z0 Core
Integer
Execution
Unit
Multiply
Unit
General Purpose
Registers
(32 x 32-bit)
Branch
Unit
Load/Store
Unit
Crossbar Switch (XBAR)
Private
Instruction
Bus
Memory Protection Unit (MPU)
FCU
Flash
(ECC)
eSCI
Peripheral Bridge
EBI
DSPI
I
2
C
FlexCAN
RAM
Controller
SRAM
(ECC)
ADC
BAM
eMIOS200
SIU
PIT
MLB
LEGEND
ADC
BAM
EBI
ECC
DSPI
eDMA
eMIOS200
eSCI
FCU
FlexCAN
– Analog to Digital Converter modules
– Boot Assist Module
– External Bus Interface module
– Error Correction Code
– Serial Peripherals Interface controller module
– enhanced Direct Memory Controller module
– Timed Input Output module
– Serial Communications Interface modules
– Flash Controller Unit
– Controller Area Network controller modules
FlexRay
– Dual Channel FlexRay controller
FMPLL
– Frequency Modulated Phase Locked Loop module
I
2
C
– Inter IC Controller modules
INTC
– Interrupt Controller module
JTAG
– Joint Test Action Group interface
MLB
– Media Local Bus emulation logic
NDI
– Nexus Debug Interface module
PIT
– Periodic Interrupt Timer module
SIU
– System Integration module
VREG
– Voltage Regulator
Figure 1. MPC5510 Family Block Diagram
MPC5510 Microcontroller Family Data Sheet, Rev. 3
Freescale Semiconductor
3
Pin Assignments and Reset States
1
1.1
Pin Assignments and Reset States
Signal Properties and Multiplexing Summary
Table 1
shows the signal properties for each pin on the MPC5510. For all port pins, which have an associated pad configuration
register (SIU_PCRn register) to control its pin properties, the “Supported Pin Functions” column lists the functions associated
with the programming of the SIU_PCRn[PA] bit field in the following order: GPIO, Function1, Function2 and Function3. If
fewer than three functions plus GPIO are supported by a given pin, then the unused functions begin with Function3, then
Function2, then Function1. Note that the GPIO number is the same number as the corresponding pad configuration register
(SIU_PCRn) number.
Table 1. MPC5510 Signal Properties
GPIO
Pin
(PCR)
Name
Num
1
Supported
Functions
2
I/O
Voltage
3
Type
Type
Pad
4
Status
During
Reset
5
Status
After
Reset
5
Package Pin
Locations
144 176 208
Description
Port A (16)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
0
1
2
3
4
5
6
7
8
9
10
11
12
13
PA0
AN0
PA1
AN1
PA2
AN2
PA3
AN3
PA4
AN4
PA5
AN5
PA6
AN6
PA7
AN7
PA8
AN8/ANW
PA9
AN9/ANX
PA10
AN10/ANY
PA11
AN11/ANZ
PA12
AN12
PA13
AN13
PA14
AN14
EXTAL32
6
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
GPI
eQADC Analog Input
32 kHz Crystal Oscillator Input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
V
DDA
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
AE + IH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
8
7
6
5
4
3
2
143
142
140
139
138
137
9
8
7
6
5
4
3
2
175
174
172
171
170
169
E3
E2
E1
D3
D2
D1
C2
C1
A3
C4
D5
C5
B5
A5
PA14
14
V
DDA
AE + IH
—
—
136
167
D6
MPC5510 Microcontroller Family Data Sheet, Rev. 3
4
Freescale Semiconductor
Pin Assignments and Reset States
Table 1. MPC5510 Signal Properties (continued)
GPIO
Pin
(PCR)
Name
Num
1
Supported
Functions
2
PA15
AN15
XTAL32
6
Description
Pad
I/O
Voltage
3
Type
Type
I
I
O
4
Status
During
Reset
5
Status
After
Reset
5
Package Pin
Locations
144 176 208
135
165
C6
PA15
15
GPI
eQADC Analog Input
32 kHz Crystal Oscillator Output
V
DDA
AE + IH
—
—
Port B (16)
PB0
AN28
eMIOS16
PCS_C5
PB1
AN29
eMIOS17
PCS_C4
PB2
AN30
eMIOS18
PCS_C3
PB3
AN31
PCS_C2
PB4
AN32
PCS_C1
PB5
AN33
PCS_C0
PB6
AN34
SCK_C
PB7
AN35
SOUT_C
PB8
AN36
SIN_C
PB9
AN37
CNTX_D
PCS_B4
PB10
AN38
CNRX_D
PCS_B3
PB11
AN39
eMIOS19
PCS_B5
GPIO
eQADC Analog Input
7
eMIOS Channel
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
eMIOS Channel
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
eMIOS Channel
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
DSPI_C Peripheral Chip Select
GPIO
eQADC Analog Input
7
DSPI_C Clock
GPIO
eQADC Analog Input
7
DSPI_C Data Output
GPIO
eQADC Analog Input
7
DSPI_C Data Input
GPIO
eQADC Analog Input
7
CAN_D Transmit
DSPI_B Peripheral Chip Select
GPIO
eQADC Analog Input
7
CAN_D Receive
DSPI_B Peripheral Chip Select
GPIO
eQADC Analog Input
7
eMIOS Channel
DSPI_B Peripheral Chip Select
I/O
I
O
O
I/O
I
O
O
I/O
I
O
O
I/O
I
O
I/O
I
O
I/O
I
I/O
I/O
I
I/O
I/O
I
O
I/O
I
I
I/O
I
O
O
I/O
I
I
O
I/O
I
O
O
PB0
16
V
DDE1
A + SH
—
—
134
162
C7
PB1
17
V
DDE1
A + SH
—
—
133
161
D7
PB2
18
V
DDE1
A + SH
—
—
132
160
A8
PB3
19
V
DDE1
A + SH
—
—
131
159
B8
PB4
20
V
DDE1
A + SH
—
—
130
158
C8
PB5
21
V
DDE1
A + SH
—
—
129
157
D8
PB6
22
V
DDE1
A + SH
—
—
128
156
A9
PB7
23
V
DDE1
A + SH
—
—
127
153
B9
PB8
24
V
DDE1
A + SH
—
—
126
152
C9
PB9
25
V
DDE1
A + SH
—
—
125
151
D9
PB10
26
V
DDE1
A + SH
—
—
124
150
A10
PB11
27
V
DDE1
A + SH
—
—
123
149
B10
MPC5510 Microcontroller Family Data Sheet, Rev. 3
Freescale Semiconductor
5
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