DATASHEET
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
Description
The IDT5P49EE801 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to eight differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional 32kHz
crystal oscillator is available to provide a real time clock or
non-critical performance MHz processor clock.
The IDT5P49EE801 can be programmed through the use
of the I
2
C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
sepctrum mode.
There are total seven 8-bit output dividers. One output bank
can be configured to support LVTTL or LVDS. All other
outputs are always set to LVTTL. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
IDT5P49EE801
Features
•
Four internal PLLs
•
Internal non-volatile EEPROM
•
Internal I
2
C EEPROM master interface
•
FAST (400kHz) mode I
2
C serial interfaces
•
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
•
Output Frequency Ranges: kHz to 120 MHz
•
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
•
8-bit output-divider blocks
•
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
•
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– Outputs - 1 pair selectable 3.3 V LVDS
•
•
•
•
•
•
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10μA max in power down mode
– 32kHz clock output active sleep mode
– 100μA max in sleep mode
•
1.8V VDD Core Voltage
•
Available in 28 pin 4x4mm QFN packages
•
-40 to +85 C Industrial Temp operation
Target Applications
•
•
•
•
•
•
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
1
IDT5P49EE801
REV M 072512
IDT5P49EE801
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Functional Block Diagram
VDD
VDDO1
VDDO2
VDDO3
S
R
C
0
XIN/REF
PLLA
XOUT
REFSEL0
/DIV0
OUT0
S
R
C
1
S
R
C
2
S
R
C
3
S
R
C
4
/DIV1
OUT1
REFSEL1
PLLB(SS)
/DIV2
OUT2
SDA
SCL
SEL[1:0]
Control
Logic
REFSEL2
PLLC
/DIV3
OUT3
/DIV4
OUT4
REFSEL3
PLLD
S
R
C
5
S
R
C
6
/DIV5
OUT5
32kXIN
OUT6A
/DIV6
OUT6B
32kXOUT
GND
Note:
OUT6A & OUT6B pair can be configured to be LVDS or two single-ended LVTTL outputs.
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
2
IDT5P49EE801
REV M 072512
IDT5P49EE801
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Pin Assignment
XIN/REF
OUT6A
XOUT
GND
VDD
SDA
VDD
OUT5
OUT4
OUT3
SEL0
VDDO1
X1_32
X2_32
1
2
3
4
5
6
7
28 27 26 25 24 23 22
21
20
19
18
17
16
15
8
VDDx
9 10 11 12 13 14
VDDO2
SEL1
GND
OUT2
VDD
GND
OUT6B
SCLK
VDDO3
OUT0
VDD
VDD
OUT1
28 pin VFQFPN
(Top View)
Pin Descriptions
Pin Name
OUT5
OUT4
OUT3
SEL0*
Pin #
1
2
3
4
5
I/O
O
O
O
I
Pin Type
Adjustable
Adjustable
Adjustable
LVTTL
Power
Pin Description
Configurable clock output 5. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configurable clock output 4. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configurable clock output 3. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configuration select pin. Weak internal pull down resistor.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT6. VDDO1
must be greater than or equal to both VDDO2 and VDDO3.
32kHz CRYSTAL_IN -- Reference crystal input
32kHz CRYSTAL_OUT -- Reference crystal feedback.
Crystal oscillator power supply. Connect to 1.8V. Use filtered
analog power supply if available.
Connect to Ground.
Connect to Ground.
Device power supply. Connect to 1.8V.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT5.
VDDO1
X132k
X232k
6
7
8
9
10
11
12
I
O
LVTTL
LVTTL
Power
Power
Power
Power
Power
VDDx
GND
GND
VDD
VDDO2
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
3
IDT5P49EE801
REV M 072512
IDT5P49EE801
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Pin Name
OUT2
SEL1*
OUT1
Pin #
13
14
15
16
17
18
19
20
21
I/O
O
I
O
Pin Type
Adjustable
LVTTL
Adjustable
Power
Power
Pin Description
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Configuration select pin. Weak internal pull down resistor.
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Device power supply. Connect to 1.8V.
Device power supply. Connect to 1.8V.
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels forOUT0-OUT5.
I
2
C clock. Logic levels set by VDDO1. 5V tolerant.
Configurable clock output 6B. Single-ended or differential when
combined with OUT6A. Output voltage levels are controlled by
VDDO1.
Configurable clock output 6A. Single-ended or differential when
combined with OUT6B. Output voltage levels are controlled by
VDDO1.
VDD
VDD
OUT0
O
Adjustable
Power
VDDO3
SCLK
OUT6B
I
O
LVTTL
Adjustable
OUT6A
22
O
Adjustable
SDA
23
24
25
26
27
I/O
Open Drain Bidirectional I
2
C data. Logic levels set by VDDO1. 5V tolerant.
Power
Power
Power
Device power supply. Connect to 1.8V.
Device power supply. Connect to 1.8V.
Connect to Ground.
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum reference clock input voltage is
1.8V.
MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
VDD
VDD
GND
XIN/ REF
I
LVTTL
XOUT
28
O
LVTTL
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Differential LVDS interface
levels can be generated for OUT4A/OUT4B when connected to VDDO1=3.3V and registers configured
appropriately. Alway completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All
other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
4
IDT5P49EE801
REV M 072512
IDT5P49EE801
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Ideal Power Up Sequence
1) V
DD
and V
DD
x must come up first, followed by V
DD
O
2) V
DD
O1 must come up within 1ms after VDD and VDDX come up
3) V
DD
O2/3 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2/3 have approx. same ramp rate
Ideal Power Down Sequence
1) V
DD
O must drop first, followed by V
DD
and V
DD
x
2) V
DD
and V
DD
x must come down within 1ms after V
DD
O1 comes down
3) V
DD
O2/3 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2/3 have approx. same ramp rate
V
V
DD
O1
V
V
DD
O1
V
DD
O2, V
DD
O3
V
DD
, V
DD
x
V
DD
O2, V
DD
O3
V
DD
, V
DD
x
1 ms
t
1 ms
t
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR
5
IDT5P49EE801
REV M 072512
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