IP4774CZ14
VGA interface with integrated h-sync buffer, ESD protection
and termination resistor
Rev. 01 — 24 February 2009
Objective data sheet
1. General description
The IP4774CZ14 is a VGA or DVI-I interface intended for connection between a video
transmitter such as a PC graphics card and a VGA or DVI-I receiver, such as a PC
monitor. The IP4774CZ14 has ESD protection for the DDC lines, ESD protection plus
buffering for the h-sync line, and high-level ESD protection diodes for the RGB video
signal lines.
The h-sync signal is buffered by a non-inverting buffer which can accept TTL-level input.
The buffer convert TTL-level input to CMOS-level output which swings between V
CC(SYNC)
and GND.
An external termination resistor can be added to achieve the desired termination, which is
typically required for the h-sync line of the video interface.
The IP4774CZ14 has a typical output resistance (R
O
) of 10
Ω.
2. Features
I
Integrated high-level ESD protection, buffering, sync-signal impedance matching
I
All pin connections have integrated rail-to-rail clamping diodes providing downstream
ESD protection of
±8
kV according to IEC 61000-4-2, level 4
I
Driver for h-sync line
I
Line capacitance < 4 pF per channel
3. Applications
Buffer and terminating channels, reduce EMI/RFI and provide downstream ESD
protection for:
I
VGA interfaces including DDC channels
I
Desktop and notebook PCs, LCD TVs and PC monitors
I
Graphics cards
I
Set-top boxes
I
Game consoles
I
DVD players
NXP Semiconductors
IP4774CZ14
VGA port protection with sync buffer
4. Ordering information
Table 1.
Ordering information
Package
Name
IP4774CZ14
SSOP14
Description
plastic shrink small outline package; 14 leads; body width 5.3 mm
Version
SOT337-1
Type number
5. Functional diagram
V
CC(VIDEO)
14
V
CC(SYNC)
9
IP4774CZ14
VIDEO_1
VIDEO_2
VIDEO_3
1
2
3
GND
10
BYP
n.c.
8
11
DDC_IN1
DDC_IN2
H_SYNC_IN
V_SYNC_IN
6
7
4
5
13
GND
12
H_SYNC_OUT
001aai178
The ESD structure of the IP4774CZ14 enables a receiver and a transmitter application.
Fig 1.
Functional diagram
IP4774CZ14_1
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 24 February 2009
2 of 12
NXP Semiconductors
IP4774CZ14
VGA port protection with sync buffer
6. Pinning information
6.1 Pinning
IP4774CZ14
VIDEO_1
VIDEO_2
VIDEO_3
H_SYNC_IN
V_SYNC_IN
DDC_IN1
DDC_IN2
1
2
3
4
5
6
7
14 V
CC(VIDEO)
13 GND
12 H_SYNC_OUT
11 n.c.
10 GND
9
8
V
CC(SYNC)
BYP
001aai179
Fig 2.
Pinning configuration
6.2 Pin description
Table 2.
Symbol
VIDEO_1
VIDEO_2
VIDEO_3
H_SYNC_IN
V_SYNC_IN
DDC_IN1
DDC_IN2
BYP
V
CC(SYNC)
GND
n.c.
H_SYNC_OUT
GND
V
CC(VIDEO)
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
ESD protection for video channel 1
ESD protection for video channel 2
ESD protection for video channel 3
h-sync signal input
h-sync protection input
DDC signal input
DDC signal input
for connecting a 100 nF bypass capacitor to increase ESD
clamping performance for the DDC outputs
supply voltage for sync buffer
ground
not connected
h-sync signal output
ground
supply voltage for video protection circuit
IP4774CZ14_1
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 24 February 2009
3 of 12
NXP Semiconductors
IP4774CZ14
VGA port protection with sync buffer
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC(SYNC)
V
I
Parameter
synchronization supply
voltage
input voltage
pins VIDEO_1, VIDEO_2, VIDEO_3
pins H_SYNC_IN, V_SYNC_IN, DDC_IN1,
DDC_IN2
V
ESD
P
tot
T
stg
[1]
Conditions
Min
GND
−
0.5
3.0
GND
−
0.5
GND
−
0.5
[1]
Max
5.5
5.5
Unit
V
V
V
CC(VIDEO)
video supply voltage
V
CC(VIDEO)
V
V
CC(SYNC)
+8
50
+125
V
kV
mW
°C
electrostatic discharge voltage IEC 61000-4-2, level 4, contact
total power dissipation
storage temperature
T
amb
= 25
°C;
f
sync
= 100 kHz; C
L
= 6 nF;
R
L
= 10 kΩ
−8
-
−55
Pins BYP, V
CC(VIDEO)
and V
CC(SYNC)
must be bypassed to pin GND via a low impedance ground plane with 100 nF.
8. Characteristics
Table 4.
Characteristics
T
amb
= 25
°
C unless otherwise specified.
Symbol
Parameter
Conditions
V
CC(VIDEO)
= 5.0 V; static input signals
V
CC(VIDEO)
= 5.0 V; f = 1 MHz; V
I
= 2.5 V (p-p);
V
bias
= 2.5 V
V
CC(VIDEO)
= 5.0 V; V
I
= V
CC(VIDEO)
or GND
I
F
= 1 mA
f = 1 MHz; V
I
= 2.5 V (p-p); V
bias
= 2.5 V
V
I
= 5.0 V
I
F
= 1 mA
[1]
[1]
Min Typ Max Unit
-
-
-
-
-
-
-
3.0
-
-
-
0.7
-
-
0.7
5.0
-
-
-
0.7
-
-
-
-
10
-
0.8
-
12
10
4
±1
-
4
±1
-
5.5
10
4
±1
-
-
0.6
µA
pF
µA
V
pF
µA
V
V
µA
pF
µA
V
V
V
V
V
Ω
ns
Analog video (RGB)
I
CC(VIDEO)
supply current on pin V
CC(VIDEO)
C
ch
I
I
V
Fd
DDC
C
ch
I
I
V
Fd
channel capacitance
input current
diode forward voltage
channel capacitance
input current
diode forward voltage
H-sync buffer
V
CC(SYNC)
synchronization supply voltage
I
CC(SYNC)
C
ch
I
I
V
Fd
V
IH
V
IL
V
OH
V
OL
R
O
t
PLH
IP4774CZ14_1
supply current on pin V
CC(SYNC)
channel capacitance
input current
diode forward voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
output resistance
V
CC(SYNC)
= 5.0 V; static input signals
V
CC(SYNC)
= 5.0 V; f = 1 MHz; V
I
= 1.65 V
V
CC(SYNC)
= 5.0 V; V
I
= 2.5 V (p-p); V
bias
= 2.5 V
I
F
= 1 mA
V
CC(SYNC)
= 5.0 V
V
CC(SYNC)
= 5.0 V
V
CC(SYNC)
= 5.0 V; I
OH
= 24 mA
V
CC(SYNC)
= 5.0 V; I
OL
= 24 mA
[2]
[1]
[1]
-
-
-
-
2.0
-
2.0
-
-
-
[3]
[3]
[3]
[3]
[3]
[1]
LOW to HIGH propagation delay V
CC(SYNC)
= 5.0 V; C
L
= 50 pF; t
r(i)
and t
f(i)
≤
5 ns
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 24 February 2009
4 of 12
NXP Semiconductors
IP4774CZ14
VGA port protection with sync buffer
Table 4.
Characteristics
…continued
T
amb
= 25
°
C unless otherwise specified.
Symbol
t
PHL
t
r(o)
t
f(o)
[1]
[2]
[3]
Parameter
output rise time
output fall time
Conditions
[1]
Min Typ Max Unit
-
-
-
4
4
12
-
-
ns
ns
ns
HIGH to LOW propagation delay V
CC(SYNC)
= 5.0 V; C
L
= 50 pF; t
r(i)
and t
f(i)
≤
5 ns
V
CC(SYNC)
= 5.0 V; C
L
= 50 pF; t
r(i)
and t
f(i)
≤
5 ns
V
CC(SYNC)
= 5.0 V; C
L
= 50 pF; t
r(i)
and t
f(i)
≤
5 ns
Guaranteed by design and characterization.
H-sync output unloaded.
These parameters apply only to the sync buffer; note that R
O
= R
buffer
.
9. Application information
The IP4774CZ14 should be placed as close as possible to the VGA or DVI-I interface
connector. The ESD-protected channels on pins VIDEO_1, VIDEO_2 and VIDEO_3 can
be connected in any order with RGB signals. The h-sync buffer is needed to have a low
jitter for the sampling PLL.
RED
GREEN
BLUE
FILTER
FILTER
FILTER
VIDEO_1
VIDEO_2
VIDEO_3
V
CC(VIDEO)
BYP
VCC_DAC
HSYNC
H_SYNC_IN
V
CC(SYNC)
GND
VCC_5V
VSYNC
V_SYNC_IN
H_SYNC_OUT
HSYNC_OUT
DDC_Clock
DDC_Data
DDC_IN1
DDC_IN2
VSYNC_OUT
IP4774CZ14
SYNC_ GND
RED
GREEN
BLUE
RGB GND
DDC_Clock
DDC_Data
001aai181
Fig 3.
Application diagram (transmitter)
The IP4774CZ14 is connected to the input lines of the VGA connector to protect the VGA
port including all signals and buffering of the h-sync signal.
IP4774CZ14_1
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 — 24 February 2009
5 of 12
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