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MT48LC8M16TG-8XT:G

Description
Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54
Categorystorage    storage   
File Size6MB,69 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT48LC8M16TG-8XT:G Overview

Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

MT48LC8M16TG-8XT:G Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeTSOP2
package instruction0.400 INCH, PLASTIC, TSOP2-54
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time7 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)125 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee0
length22.22 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature75 °C
Minimum operating temperature-25 °C
organize8MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)235
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.00045 A
Maximum slew rate0.21 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width10.16 mm
128Mb: x16, x32
MOBILE SDRAM
SYNCHRONOUS
DRAM
Features
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT auto
precharge, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial Array Self Refresh power-saving mode
MT48LC8M16LFF4, MT48V8M16LFF4,
MT48LC8M16TG, MT48V8M16TG,
MT48V8M16P, MT48LC4M32LFF5,
MT48V4M32LFF5
Table 1:
Configuration
Refresh Count
Row Addressing
Bank
Addressing
Column
Addressing
Configurations
8 MEG X 16
2 Meg x 16 x 4
banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
4 MEG X 32
1 Meg x 32 x 4
banks
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
Table 2:
Key Timing Parameters
Options
• V
DD
/V
DD
Q
3.3V/3.3V
2.5V/2.5V – 1.8V
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package/Ball out
54-ball VFBGA (8mm x 8mm)
1
54-ball VFBGA (8mm x 8mm)
1
Lead-Free
90-ball VFBGA (8mm x 13mm)
2
90-ball VFBGA (8mm x 13mm)
2
Lead-Free
54-Pin TSOP II (400 mil)
54-Pin TSOP II (400 mil) Lead-Free
• Timing (Cycle Time)
7.5ns @ CL = 3 (133 MHz)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
• Temperature
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Extended (-25°C to +75°C)
• Design Revision
NOTE:
1. x16 only.
2. x32 only.
Marking
LC
V
8M16
4M32
F4
B4
F5
B5
TG
P
-75M
-8
-10
None
IT
XT
:G
CL = CAS (READ) latency
ACCESS TIME
SPEED
CLOCK
GRADE FREQUENCY CL = 1 CL = 2 CL = 3
t
RCD
-75M
-8
-10
-75M
-8
-10
-8
-10
133MHz
125 MHz
100 MHz
100MHz
100 MHz
83 MHz
50 MHz
40 MHz
-
-
19ns
22ns
-
6
8ns
8ns
5.4
7ns
7ns
-
19ns
20ns
20ns
19ns
20ns
20ns
20ns
20ns
t
RP
19ns
20ns
20ns
19ns
20ns
20ns
20ns
20ns
Part Number Example:
MT48V8M16LFB4-8
09005aef8071a76b
128Mbx16x32Mobile_1.fm - Rev. J 5/05 EN
1
©2001 Micron Technology, Inc. All rights reserved.
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