Maximum Junction Temperature (Plastic Package). . . . . . . . . 150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
DC Operating Characteristics – RTC
Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD
V
BAT
I
DD1
PARAMETER
Main Power Supply
Battery Supply Voltage
Supply Current
V
DD
= 5V
V
DD
= 3V
I
DD2
I
DD3
I
BAT
I
BATLKG
I
LI
I
LO
V
TRIP
V
TRIPHYS
V
BATHYS
IRQ/F
OUT
V
OL
Output Low Voltage
V
DD
= 5V, I
OL
= 3mA
V
DD
= 2.7V, I
OL
= 1mA
I
LO
Output Leakage Current
V
DD
= 5.5V
V
OUT
= 5.5V
100
0.4
0.4
400
V
V
nA
Supply Current With I
2
C Active
Supply Current (Low Power Mode)
Battery Supply Current
Battery Input Leakage
Input Leakage Current on SCL
I/O Leakage Current on SDA
V
BAT
Mode Threshold
V
TRIP
Hysteresis
V
BAT
Hysteresis
1.6
10
10
V
DD
= 5V
V
DD
= 5V, LPMODE = 1
V
BAT
= 3V
V
DD
= 5.5V, V
BAT
= 1.8V
100
100
2.2
35
50
2.64
60
100
CONDITIONS
MIN
2.7
1.8
2
1.2
40
1.4
400
TYP
(Note 5)
MAX
5.5
5.5
6
4
120
5
950
100
UNITS
V
V
µA
µA
µA
µA
nA
nA
nA
nA
V
mV
mV
2, 3
2, 7
2
2, 3
NOTES
Power-Down Timing
Temperature = -40°C to +85°C, unless otherwise stated.
SYMBOL
V
DD SR-
PARAMETER
V
DD
Negative Slewrate
CONDITIONS
MIN
TYP
(Note 5)
MAX
10
UNITS
V/ms
NOTES
4
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 5)
MAX
UNITS
NOTES
SERIAL INTERFACE SPECS
V
IL
V
IH
SDA and SCL Input Buffer LOW
Voltage
SDA and SCL Input Buffer HIGH
Voltage
-0.3
0.7 x
V
DD
0.3 x
V
DD
V
DD
+
0.3
V
V
3
FN6313.0
June 22, 2006
ISL1218
Serial Interface Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
Hysteresis
V
OL
Cpin
f
SCL
t
IN
t
AA
PARAMETER
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec
and SCL Inputs
is suppressed.
SCL Falling Edge to SDA Output Data
Valid
Time the Bus Must be Free before the
Start of a New Transmission
SCL falling edge crossing 30% of V
DD
,
until SDA exits the 30% to 70% of V
DD
window.
SDA crossing 70% of V
DD
during a
STOP condition, to SDA crossing 70%
of V
DD
during the following START
condition.
Measured at the 30% of V
DD
crossing.
Measured at the 70% of V
DD
crossing.
SCL rising edge to SDA falling edge.
Both crossing 70% of V
DD
.
From SDA falling edge crossing 30% of
V
DD
to SCL falling edge crossing 70%
of V
DD
.
From SDA exiting the 30% to 70% of
V
DD
window, to SCL rising edge
crossing 30% of V
DD
From SCL falling edge crossing 30% of
V
DD
to SDA entering the 30% to 70%
of V
DD
window.
From SCL rising edge crossing 70% of
V
DD
, to SDA rising edge crossing 30%
of V
DD
.
From SDA rising edge to SCL falling
edge. Both crossing 70% of V
DD
.
From SCL falling edge crossing 30% of
V
DD
, until SDA enters the 30% to 70%
of V
DD
window.
From 30% to 70% of V
DD
From 70% to 30% of V
DD
Total on-chip and off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1300
T
A
= 25°C, f = 1MHz, V
DD
= 5V,
V
IN
= 0V, V
OUT
= 0V
TEST CONDITIONS
MIN
0.05 x
V
DD
0
0.4
10
400
50
900
TYP
(Note 5)
MAX
UNITS
V
V
pF
kHz
ns
ns
NOTES
t
BUF
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
1300
600
600
600
ns
ns
ns
ns
t
SU:DAT
Input daTa Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
900
ns
t
SU:STO
STOP Condition Setup Time
600
ns
t
HD:STO
t
DH
STOP Condition Hold Time
Output Data Hold Time
600
0
ns
ns
t
R
t
F
Cb
Rpu
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-up Resistor
Off-chip
20 +
0.1 x Cb
20 +
0.1 x Cb
10
1
300
300
400
ns
ns
pF
kΩ
6
6
6
6
NOTES:
2. IRQ and F
OUT
Inactive.
3. LPMODE = 0 (default).
4. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
5. Typical values are for T = 25°C and 3.3V supply voltage.
6. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
7. A write to register 08h should only be done if V
DD
> V
BAT
, otherwise the device will be unable to communicate using I
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