Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Leakage Current
GND < V
I
< V
CC
Output Leakage Current GND < V
I
< V
CC
,
Output Disabled
V
CC
Operating
Supply Current
Automatic CE
Power- Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
= – 4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–5
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
140
40
2.2
–0.3
–1
–5
Max.
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+5
130
40
-15
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
10
10
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 480Ω
R1 480Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤
3 ns
3.0V
90%
10%
90%
10%
≤
3 ns
ALL INPUT PULSES
Equivalent to: THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05026 Rev. *C
Page 2 of 8
CY7C1019B
Switching Characteristics
[4]
Over the Operating Range
-12
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[7, 8]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
12
9
8
0
0
8
6
0
3
6
15
10
10
0
0
10
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
0
12
3
6
0
15
0
6
3
7
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-15
Max.
Unit
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05026 Rev. *C
Page 3 of 8
CY7C1019B
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
[10, 11]
ADDRESS
t
RC
CE
t
ACE
OE
t
DOE
DATA OUT
V
CC
SUPPLY
CURRENT
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
ISB
ICC
HIGH
IMPEDANCE
Notes:
9. Device is continuously selected. OE, CE = V
IL
.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05026 Rev. *C
Page 4 of 8
CY7C1019B
Switching Waveforms
(continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
t
WC
ADDRESS
t
SCE
CE
t
SA
t
SCE
t
AW
t
PWE
WE
t
SD
DATA I/O
DATA VALID
t
HD
t
HA
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[12, 13]
t
WC
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
t
PWE
t
HA
OE
t
SD
DATA I/O
NOTE 14
t
HZOE
Notes:
12. Data I/O is high impedance if OE = V
IH
.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
I would like to ask you guys, what is wrong with this switch circuit, how to pull it down at the G pole, is there a problem somewhere else? What needs to be improved?...
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