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Data Sheet
FEATURES
Fast settling filter option
4 differential/8 pseudo differential input channels
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Specified drift over time
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AV
DD
: 3 V to 5.25 V
DV
DD
: 2.7 V to 5.25 V
Current: 4.65 mA
Temperature range: −40°C to +105°C
28-lead TSSOP and 32-lead LFCSP packages
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
4-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
AD7193
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7193 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have four differential inputs or
eight pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled simultaneously, and the
AD7193 sequentially converts on each enabled channel, simplifying
communication with the part. The on-chip 4.92 MHz clock can
be used as the clock source to the ADC or, alternatively, an external
clock or crystal can be used. The output data rate from the part
can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. The AD7193 also
includes a zero latency option.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is available in a 28-lead
TSSOP package and a 32-lead LFCSP package.
APPLICATIONS
PLC/DCS analog input modules
Data acquisition
Strain gage transducers
AV
DD
AGND
DV
DD
DGND
FUNCTIONAL BLOCK DIAGRAM
REFIN1(+)
REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AINCOM
AD7193
MUX
PGA
Σ-Δ
ADC
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
SYNC
TEMP
SENSOR
BPDSW
CLOCK
CIRCUITRY
P3
P2
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
Figure 1.
Rev. D
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08367-001
AGND
AD7193
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
RMS Noise and Resolution............................................................ 18
Sinc
4
Chop Disabled ................................................................... 18
Sinc
3
Chop Disabled ................................................................... 19
Fast Settling ................................................................................. 20
On-Chip Registers .......................................................................... 21
Communications Register ......................................................... 22
Status Register ............................................................................. 23
Mode Register ............................................................................. 24
Configuration Register .............................................................. 27
Data Register ............................................................................... 29
ID Register ................................................................................... 29
GPOCON Register ..................................................................... 29
Offset Register............................................................................. 30
Full-Scale Register ...................................................................... 30
ADC Circuit Information .............................................................. 31
Overview...................................................................................... 31
Analog Input Channel ............................................................... 32
Programmable Gain Array (PGA) ........................................... 32
Data Sheet
Reference ..................................................................................... 32
Reference Detect ......................................................................... 33
Bipolar/Unipolar Configuration .............................................. 33
Data Output Coding .................................................................. 33
Burnout Currents ....................................................................... 33
Channel Sequencer .................................................................... 33
Digital Interface .......................................................................... 34
Reset ............................................................................................. 38
System Synchronization ............................................................ 38
Enable Parity ............................................................................... 38
Clock ............................................................................................ 38
Bridge Power-Down Switch ...................................................... 38
Temperature Sensor ................................................................... 39
Logic Outputs ............................................................................. 39
Calibration................................................................................... 39
Digital Filter .................................................................................... 41
Sinc
4
Filter (Chop Disabled) ..................................................... 41
Sinc
3
Filter (Chop Disabled) ..................................................... 43
Chop Enabled (Sinc
4
Filter) ...................................................... 45
Chop Enabled (Sinc
3
Filter) ...................................................... 47
Fast Settling Mode (Sinc
4
Filter) ............................................... 48
Fast Settling Mode (Sinc
3
Filter) ............................................... 50
Fast Settling Mode (Chop Enabled)......................................... 51
Summary of Filter Options ....................................................... 52
Grounding and Layout .................................................................. 53
Applications Information .............................................................. 54
Flowmeter.................................................................................... 54
Outline Dimensions ....................................................................... 55
Ordering Guide .......................................................................... 55
Rev. D | Page 2 of 56
Data Sheet
REVISION HISTORY
3/13—Rev. C to Rev. D
Changes to CON2 to CON0 Description; Table 22 ....................28
Changes to Equations in Data Output Coding Section .............33
12/11—Rev. B to Rev. C
Moved Revision History Section ..................................................... 3
Changes to Table 6 ..........................................................................13
4/10—Rev. A to Rev. B
Added 32-Lead LFCSP ...................................................... Universal
Changes to Table 7 ..........................................................................17
Changes to Communications Register, Table 16 .........................20
Updated Outline Dimensions ........................................................54
Changes to Ordering Guide ...........................................................54
9/09—Rev. 0 to Rev. A
AD7193
Changes to Internal/External Clock, Internal Clock Frequency
Parameter, Table 1 ............................................................................. 5
Changes to Figure 7 and Figure 8 ................................................. 14
Changes to Table 6 .......................................................................... 17
Changes to Table 9 .......................................................................... 18
Changes to Table 12, Table 13, and Table 14 ............................... 19
Changes to Table 19 ........................................................................ 24
Changes to Table 22 and Table 23 ................................................. 27
Changes to Offset Register and Full-Scale Register Sections .... 29
Changes to Reference Section ....................................................... 31
Changes to Data Output Coding Section .................................... 32
Changes to Sinc
4
50 Hz/60 Hz Rejection Section ....................... 41
Changes to Sinc
3
50 Hz/60 Hz Rejection Section ....................... 43
Changes to 50 Hz/60 Hz Rejection, Sinc
4
Filter Section ............ 47
Changes to Summary of Filter Options Section and Table 35 .. 52
7/09—Revision 0: Initial Version
Rev. D | Page 3 of 56
AD7193
SPECIFICATIONS
Data Sheet
AV
DD
= 3 V to 5.25 V, DV
DD
= 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = 2.5 V or AV
DD
, REFINx(−) = AGND,
MCLK = 4.92 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
ADC
Output Data Rate
Min
4.7
1.17
1.56
24
24
Typ
Max
4800
1200
1600
Unit
Hz
Hz
Hz
Bits
Bits
Test Conditions/Comments
1
Chop disabled
Chop enabled, sinc
4
filter
Chop enabled, sinc
3
filter
FS[9:0]
3
> 1, sinc
4
filter
FS[9:0]
3
> 4, sinc
3
filter
See the RMS Noise and Resolution section
See the RMS Noise and Resolution section
No Missing Codes
2
Resolution
RMS Noise and Output
Data Rates
Integral Nonlinearity
Gain = 1
2
Gain > 1
Offset Error
4, 5
Offset Error Drift vs.
Temperature
±2
±2
±5
±15
±150/gain
±1
±0.5
±150/gain
±5
±5
25
±0.001
−0.39
±0.003
±0.005
±10
±15
±30
±30
ppm of FSR
ppm of FSR
ppm of FSR
ppm of FSR
µV
µV
µV
nV/°C
nV/°C
nV/°C
nV/1000
hours
%
%
%
%
ppm/°C
ppm/
1000 hours
dB
dB
dB
dB
dB
dB
dB
dB
dB
AV
DD
= 5 V
AV
DD
= 3 V
AV
DD
= 5 V
AV
DD
= 3 V
Chop disabled
Chop enabled, AV
DD
= 5 V
Chop enabled, AV
DD
= 3 V
Gain = 1 to 16; chop disabled
Gain = 32 to 128; chop disabled
Chop enabled
Gain > 32
AV
DD
= 5 V, gain = 1, T
A
= 25°C
(factory calibration conditions)
Gain = 128, before full-scale calibration
(see Table 27)
Gain > 1, after internal full-scale calibration,
AV
DD
≥ 4.75 V
Gain > 1, after internal full-scale calibration,
AV
DD
< 4.75 V
Offset Error Drift vs. Time
Gain Error
4
Gain Drift vs.
Temperature
Gain Drift vs. Time
Power Supply Rejection
95
Common-Mode Rejection
@ DC
@ DC
@ 50 Hz, 60 Hz
2
@ 50 Hz
2
@ 60 Hz
2
±1
10
90
110
110
105
120
120
120
115
115
Gain = 1
Gain = 1, V
IN
= 1 V
Gain > 1, V
IN
= 1 V/gain
Gain = 1, V
IN
= 1 V
Gain > 1, V
IN
= 1 V/gain
10 Hz output data rate, 50 Hz ± 1 Hz,
60 Hz ± 1 Hz
50 Hz output data rate, 50 Hz ± 1 Hz
60 Hz output data rate, 60 Hz ± 1 Hz
Fast settling, FS[9:0]
3
= 6, average by 16,
50 Hz ± 1 Hz
Fast settling, FS[9:0]
3
= 5, average by 16,
60 Hz ± 1 Hz
@ 50 Hz
2
@ 60 Hz
2
Rev. D | Page 4 of 56
Analog electronics
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