1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
2004 Mar 03
3
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC68692
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
TxDA
R/WN
DTACKN
CSN
A1–A4
RESETN
4
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
RECEIVE
HOLDING REG (3)
RxDA
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
INTERRUPT CONTROL
INTRN
IMR
IACKN
ISR
IVR
INTERNAL DATABUS
CHANNEL B
(AS ABOVE)
TxDB
RxDB
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
CONTROL
TIMING
BAUD RATE
GENERATOR
TIMING
6
IP0-IP5
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
X1/CLK
XTAL OSC
X2
CSRA
CSRB
ACR
CTUR
CTLR
OP0-OP7
OPCR
OPR
V
CC
GND
SD00145
Figure 2. Block Diagram
2004 Mar 03
4
Philips Semiconductors
Product data
Dual asynchronous receiver/transmitter (DUART)
SCC68692
PIN DESCRIPTION
SYMBOL
D0–D7
CSN
PIN NO.
TYPE
25,16,24,17
I/O
23,18,22,19
35
I
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
Chip Enable:
Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are
enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is HIGH, the DUART places
the D0–D7 lines in the 3-State condition.
Read/Write:
A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Address Inputs:
Select the DUART internal registers and ports for read/write operations.
Reset:
A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex
0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (HIGH) state. Resets Test Mode, sets MR pointer to MR1.
Data Transfer Acknowledge:
3-State active-LOW output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
Interrupt Request:
Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
Interrupt Acknowledge:
Active-LOW input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
Crystal 2:
Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected
although it is permissible to ground it.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel B Receive Serial Data Input:
The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is HIGH, “space” is LOW.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
Output 0:
General purpose output or Channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 2:
General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
Output 3:
General purpose output or open-drain, active-LOW counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
Output 4:
General purpose output or Channel A open-drain, active-LOW, RxRDYAN/FFULLAN output.
Output 5:
General purpose output or Channel B open-drain, active-LOW, RxRDYBN/FFULLBN output.
Output 6:
General purpose output or Channel A open-drain, active-LOW, TxRDYAN output.
Output 7:
General purpose output or Channel B open-drain, active-LOW, TxRDYBN output.
Input 0:
General purpose input or Channel A clear to send active-LOW input (CTSAN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 1:
General purpose input or Channel B clear to send active-LOW input (CTSBN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 2:
General purpose input or Channel B receiver external clock input (RxCB), or counter/timer external
clock input. When external clock is used by the receiver, the received data is sampled on the rising edge of
the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA). When the external clock
is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal
V
CC
pull-up device supplying 1 to 4
µA
of current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
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