A42MX16-2PL84MX79 datasheet, PDF

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A42MX16-2PL84MX79: DescriptionField Programmable Gate Array, 608 CLBs, 24000 Gates, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size880KB，123 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

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A42MX16-2PL84MX79 Overview

Field Programmable Gate Array, 608 CLBs, 24000 Gates, CMOS, PQCC84, PLASTIC, LCC-84

A42MX16-2PL84MX79 Parametric

Parameter Name	Attribute value
Maker	Microsemi
package instruction	QCCJ,
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Other features	CAN ALSO BE OPERATED AT 3.3V I/O SUPPLY
Combined latency of CLB-Max	2 ns
JESD-30 code	S-PQCC-J84
length	29.3116 mm
Configurable number of logic blocks	608
Equivalent number of gates	24000
Number of terminals	84
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	608 CLBS, 24000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.3116 mm

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v6.0

40MX and 42MX FPGA Families

Features

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

HiRel Features

•

Commercial, Industrial, Automotive, and Military

Temperature Plastic Packages

Commercial, Military Temperature, and MIL-STD-883

Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Ease of Integration

•

Mixed-Voltage Operation (5.0V or 3.3V for core and

I/Os), with PCI-Compliant I/Os

Up to 100% Resource Utilization and 100% Pin

Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

High Performance

•

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

Product Profile

Device

Capacity

System Gates

SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

Clock-to-Out

SRAM Modules

(64x4 or 32x8)

Dedicated Flip-Flops

Maximum Flip-Flops

Clocks

User I/O (maximum)

PCI

Boundary Scan Test (BST)

Packages (by pin count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

A40MX02

3,000

–

295

–

9.5 ns

–

147

–

44, 68

100

–

A40MX04

6,000

–

547

–

9.5 ns

–

273

–

44, 68, 84

100

–

A42MX09

14,000

–

348

336

–

5.6 ns

–

348

516

104

–

100, 160

100

176

–

A42MX16

24,000

–

624

608

–

6.1 ns

–

624

928

140

–

100, 160, 208

100

176

–

A42MX24

36,000

–

954

912

6.1 ns

–

954

1,410

176

Yes

160, 208

–

176

–

A42MX36

54,000

2,560

1,230

1,184

6.3 ns

1,230

1,822

202

Yes

–

208, 240

–

208, 256

272

January 2004

See the Actel website (www.actel.com) for the latest version of this datasheet.

40MX and 42MX FPGA Families

Table of Contents

40MX and 42MX FPGA Families

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18

Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19

Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

Parameter Measurement

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77

Package Pin Assignments

44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

v6.0

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