M59DR008E
M59DR008F
8 Mbit (512Kb x16, Dual Bank, Page)
1.8V Supply Flash Memory
s
SUPPLY VOLTAGE
– V
DD
= V
DDQ
= 1.65V to 2.2V for Program,
Erase and Read
– V
PP
= 12V for fast Program (optional)
s
ASYNCHRONOUS PAGE MODE READ
– Page Width: 4 words
– Page Access: 35ns
– Random Access: 100ns
BGA
s
PROGRAMMING TIME
– 10µs by Word typical
– Double Word Programming Option
TSOP48 (N)
12 x 20mm
TFBGA48 (ZB)
8 x 6 balls array
s
MEMORY BLOCKS
– Dual Bank Memory Array: 4 Mbit - 4 Mbit
– Parameter Blocks (Top or Bottom location)
Figure 1. Logic Diagram
s
DUAL BANK OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s
BLOCK PROTECTION/UNPROTECTION
– All Blocks protected at Power Up
– Any combination of Blocks can be protected
19
A0-A18
W
E
G
RP
WP
VDD VDDQ VPP
16
DQ0-DQ15
s
s
s
s
COMMON FLASH INTERFACE (CFI)
64 bit SECURITY CODE
ERASE SUSPEND and RESUME MODES
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M59DR008E: A2h
– Bottom Device Code, M59DR008F: A3h
M59DR008E
M59DR008F
s
VSS
AI03212
June 2001
1/38
M59DR008E, M59DR008F
Figure 2. TFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP
NC
A7
A4
B
A14
A10
W
RP
A18
A17
A5
A2
C
A15
A12
A9
NC
NC
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E
A0
E
VDDQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VDD
DQ10
DQ1
G
AI03213B
Figure 3. TSOP Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
VPP
WP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
A16
VDDQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Table 1. Signal Names
A0-A18
DQ0-DQ15
E
G
W
RP
WP
V
DD
V
DDQ
V
PP
V
SS
NC
Address Inputs
Data Input/Outputs, Command Inputs
Chip Enable
Output Enable
Write Enable
Reset/Power Down
Write Protect
Supply Voltage
Supply Voltage for Input/Output
Buffers
Optional Supply Voltage for
Fast Program & Erase
Ground
Not Connected Internally
12 M59DR008E 37
13 M59DR008F 36
24
25
AI03214
2/38
M59DR008E, M59DR008F
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (3)
V
DD
, V
DDQ
V
PP
Parameter
Ambient Operating Temperature
(2)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Program Voltage
Value
–40 to 85
–40 to 125
–55 to 155
–0.5 to V
DDQ
+0.5
–0.5 to 2.7
–0.5 to 13
Unit
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Depends on range.
3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
DESCRIPTION
The M59DR008 is an 8 Mbit non-volatile Flash
memory that may be erased electrically at block
level and programmed in-system on a Word-by-
Word basis using a 1.65V to 2.2V V
DD
supply for
the circuitry. For Program and Erase operations
the necessary high voltages are generated inter-
nally. The device supports asynchronous page
mode from all the blocks of the memory array.
The array matrix organization allows each block to
be erased and reprogrammed without affecting
other blocks. All blocks are protected against pro-
gramming and erase at Power Up. Blocks can be
unprotected to make changes in the application
and then reprotected.
Instructions for Read/Reset, Auto Select, Write
Configuration Register, Programming, Block
Erase, Bank Erase, Erase Suspend, Erase Re-
sume, Block Protect, Block Unprotect, Block Lock-
ing, CFI Query, are written to the memory through
a Command Interface using standard micropro-
cessor write timings.
The device is offered in TSOP48 (12 x 20 mm)
and in TFBGA48 (0.75 mm pitch) packages and it
is supplied with all the bits erased (set to ‘1’).
Organization
The M59DR008 is organized as 512Kb x16 bits.
A0-A18 are the address lines, DQ0-DQ15 are the
Data Input/Output. Memory control is provided by
Chip Enable E, Output Enable G and Write Enable
W inputs.
Reset RP is used to reset all the memory circuitry
and to set the chip in power down mode if this
function is enabled by a proper setting of the Con-
figuration Register. Erase and Program operations
are controlled by an internal Program/Erase Con-
troller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, DQ6 and DQ2
provide Toggle signals and DQ5 provides error bit
to indicate the state of the P/E.C operations.
Memory Blocks
The device features asymmetrically blocked archi-
tecture. M59DR008 has an array of 23 blocks and
is divided into two banks A and B, providing Dual
Bank operations. While programming or erasing in
Bank A, read operations are possible into Bank B
or vice versa. The memory also features an erase
suspend allowing to read or program in another
block within the same bank. Once suspended the
erase can be resumed. The Bank Size and Sector-
ization are summarized in Table 7. Parameter
Blocks are located at the top of the memory ad-
dress space for the M59DR008E, and at the bot-
tom for the M59DR008F. The memory maps are
shown in Tables 3, 4, 5 and 6.
The Program and Erase operations are managed
automatically by the P/E.C. Block protection
against Program or Erase provides additional data
security. All blocks are protected at Power Up. In-
structions are provided to protect or unprotect any
block in the application. A second register locks
the protection status while WP is low (see Block
Locking description). The Reset command does
not affect the configuration of unprotected blocks
and the Configuration Register status.
3/38
M59DR008E, M59DR008F
Table 3. Bank A, Top Boot Block Addresses
M59DR008E
#
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Size
(KWord)
4
4
4
4
4
4
4
4
32
32
32
32
32
32
32
Address Range
7F000-7FFFF
7E000-7EFFF
7D000-7DFFF
7C000-7CFFF
7B000-7BFFF
7A000-7AFFF
79000-79FFF
78000-78FFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
14
13
12
11
Table 5. Bank B, Bottom Boot Block Addresses
M59DR008F
#
7
6
5
4
3
2
1
0
Size
(KWord)
32
32
32
32
32
32
32
32
Address Range
78000-7FFFF
70000-77FFF
68000-6FFFF
60000-67FFF
58000-5FFFF
50000-57FFF
48000-4FFFF
40000-47FFF
Table 6. Bank A, Bottom Boot Block Addresess
M59DR008F
#
Size
(KWord)
32
32
32
32
32
32
32
4
4
4
4
4
4
4
4
Address Range
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
07000-07FFF
06000-06FFF
05000-05FFF
04000-04FFF
03000-03FFF
02000-02FFF
01000-01FFF
00000-00FFF
Table 4. Bank B, Top Boot Block Addresses
M59DR008E
#
7
6
5
4
3
2
1
0
Size
(KWord)
32
32
32
32
32
32
32
32
Address Range
38000-3FFFF
30000-37FFF
28000-2FFFF
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF
00000-07FFF
10
9
8
7
6
5
4
3
2
1
0
4/38
M59DR008E, M59DR008F
Table 7. Bank Size and Sectorization
Bank Size
Bank A
Bank B
4 Mbit
4 Mbit
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
7 blocks of 32 KWord
8 blocks of 32 KWord
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A18).
The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W, whichever occurs last.
Data Input/Output (DQ0-DQ15).
The Input is
data to be programmed in the memory array or a
command to be written to the Command Interface
(C.I.) Both input data and commands are latched
on the rising edge of Write Enable W. The Ouput
is data from the Memory Array, the Common Flash
Interface, the Electronic Signature Manufacturer
or Device codes, the Block Protection status, the
Configuration Register status or the Status Regis-
ter Data Polling bit DQ7, the Toggle Bits DQ6 and
DQ2, the Error bit DQ5. The data bus is high im-
pedance when the chip is deselected, Output En-
able G is at V
IH
, or RP is at V
IL
.
Chip Enable (E).
The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E at V
IH
deselects
the memory and reduces the power consumption
to the standby level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at V
IL
.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is at V
IH
the outputs are High im-
pedance.
Write Enable (W).
This input controls writing to
the Command Register and Data latches. Data are
latched on the rising edge of W.
Write Protect (WP).
This input gives an addition-
al hardware protection level against program or
erase when pulled at V
IL
, as described in the Block
Lock instruction description.
Reset/Power Down Input (RP).
The RP input
provides hardware reset of the memory (without
affecting the Configuration Register status), and/
or Power Down functions, depending on the Con-
figuration Register status. Reset/Power Down of
the memory is achieved by pulling RP to V
IL
for at
least t
PLPH
. When the reset pulse is given, if the
memory is in Read, Erase Suspend Read or
Standby, it will output new valid data in t
PHQ7V1
af-
ter the rising edge of RP. If the memory is in Erase
or Program modes, the operation will be aborted
and the reset recovery will take a maximum ot
t
PLQ7V
. The memory will recover from Power
Down (when enabled) in t
PHQ7V2
after the rising
edge of RP. See Tables 24, 26 and Figure 10.
V
DD
and V
DDQ
Supply Voltage (1.65V to 2.2V).
The main power supply for all operations (Read,
Program and Erase). V
DD
and V
DDQ
must be at
the same voltage.
V
PP
Programming Voltage (11.4V to 12.6V).
Used
to provide high voltage for fast factory program-
ming. High voltage on V
PP
pin is required to use
the Double Word Program instruction. It is also
possible to perform word program or erase instruc-
tions with V
PP
pin grounded.
V
SS
Ground.
V
SS
is the reference for all the volt-
age measurements.
DEVICE OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Read Array (Random,
and Page Modes), Write command, Output Dis-
able, Standby, Reset/Power Down and Block
Locking. See Table 8.
Read.
Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register, the CFI, the Block
Protection Status or the Configuration Register
status. Read operation of the memory array is per-
formed in asynchronous page mode, that provides
fast access time. Data is internally read and stored
in a page buffer. The page has a size of 4 words
and is addressed by A0-A1 address inputs. Read
operations of the Electronic Signature, the Status
Register, the CFI, the Block Protection Status, the
Configuration Register status and the Security
Code are performed as single asyncronous read
cycles (Random Read). Both Chip Enable E and
Output Enable G must be at V
IL
in order to read the
output of the memory.
Write.
Write operations are used to give Instruc-
tion Commands to the memory or to latch Input
Data to be programmed. A write operation is initi-
ated when Chip Enable E and Write Enable W are
at V
IL
with Output Enable G at V
IH
. Addresses are
latched on the falling edge of W or E whichever oc-
curs last. Commands and Input Data are latched
on the rising edge of W or E whichever occurs first.
Noise pulses of less than 5ns typical on E, W and
G signals do not start a write cycle.
5/38
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