Edge-rate control circuitry for significantly improved
noise characteristics
•
Typical output skew < 250 ps
•
ESD > 2000V
•
TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
•
Industrial temperature range of –40°C to +85°C
•
V
CC
= 5V
±
10%
•
Eliminates the need for external pull-up or pull-down
resistors
Functional Description
These 16-bit registered transceivers are high-speed,
low-power devices. 16-bit operation is achieved by connecting
the control lines of the two 8-bit registered transceivers
together. For data flow from bus A-to-B, CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when OEAB is LOW. Control of data from B-to-A is similar and
is controlled by using the CEBA, CLKBA, and OEBA inputs.
The output buffers are designed with a power-off disable
feature to allow for live insertion of boards.
The CY74FCT16952T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162952T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162952T is ideal for driving transmission lines.
The CY74FCT162H952T is a 24-mA balanced output part that
has “bus hold” on the data inputs. The device retains the
input’s last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents floating inputs.
CY74FCT16952T Features:
•
64 mA sink current, 32 mA source current
•
Typical V
OLP
(ground bounce) <1.0V at
V
CC
= 5V, T
A
= 25°C
CY74FCT162952T Features:
•
Balanced 24 mA output drivers
•
Reduced system switching noise
•
Typical V
OLP
(ground bounce) <0.6V at
V
CC
= 5V, T
A
= 25°C
CY74FCT162H952T Features:
•
Bus hold retains last active state
Logic Block Diagrams
Pin Configuration
SSOP/TSSOP
Top View
1
OEAB
1
CEBA
1
CLKBA
1
OEAB
1
CEAB
1
CLKAB
1
OEBA
1
A
1
2
CEBA
2
CLKBA
2
OEAB
2
CEAB
2
CLKAB
2
OEBA
1
CLKAB
1
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
CEBA
GND
1
A
1
1
A
2
V
CC
1
A
3
1
A
4
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
C
CE
D
C
CE
D
1
B
1
2
A
1
C
CE
D
C
CE
D
1
A
5
2
B
GND
1
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
FCT16952–1
FCT16952–2
2
A
3
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
GND
2
A
4
2
A
5
2
A
6
V
CC
2
A
7
2
A
8
GND
2
B
4
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
FCT16952–3
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
August 1994 – Revised October 30, 1997
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Pin Description
Name
OEAB
OEBA
CEAB
CEBA
CLKAB
CLKBA
A
B
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A Three-State
Outputs
[1]
B-to-A Data Inputs or A-to-B Three-State
Outputs
[1]
Maximum Ratings
[5, 6]
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Storage Temperature ................................. –55°C to +125°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
DC Input Voltage ............................................–0.5V to +7.0V
DC Output Voltage..........................................–0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin) ........................ –60 to +120 mA
Power Dissipation .......................................................... 1.0W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Function Table
[2, 3]
For A-to-B (Symmetric with B-to-A)
Inputs
CEAB
H
X
L
L
X
X
CLKAB
X
L
OEAB
L
L
L
L
H
A
X
X
L
H
X
Outputs
B
B
[4]
Operating Range
Range
Industrial
Ambient
Temperature
–40°C to +85°C
V
CC
5V
±
10%
B
[4]
L
H
Z
Notes:
1. On the CY74FCT162H952T these pins have bus hold.
2. A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA.
3. H = HIGH Voltage Level.
L = LOW Voltage Level.
X = Don’t Care.
= LOW-to-HIGH Transition.
Z = HIGH Impedance.
Level of B before the indicated steady-state input conditions were established.
Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4.
5.
6.
2
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Electrical Characteristics
Over the Operating Range
Parameter
V
IH
V
IL
V
H
V
IK
I
IH
I
IL
I
BBH
I
BBL
I
BHHO
I
BHLO
I
OZH
I
OZL
I
OS
I
O
I
OFF
Description
Input HIGH Voltage
Input LOW Voltage
Input Hysteresis
[8]
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
Standard
Bus Hold
Standard
Bus Hold
Bus Hold Sustain Current on Bus Hold Input
[9]
V
CC
=Min.
V
I
=2.0V
V
I
=0.8V
Bus Hold Overdrive Current on Bus Hold Input
[9]
V
CC
=Max., V
I
=1.5V
High Impedance Output Current (Three-State
Output pins)
High Impedance Output Current (Three-State
Output pins)
Short Circuit Current
[10]
Output Drive Current
Power-Off Disable
[10]
Test Conditions
Min.
2.0
Typ.
[7]
Max.
0.8
Unit
V
V
mV
V
µA
µA
µA
µA
µA
100
V
CC
=Min., I
IN
= –18 mA
V
CC
=Max., V
I
=V
CC
V
CC
=Max., V
I
=GND
–50
+50
TBD
±1
±1
–80
–50
–140
–200
–180
±1
–0.7
–1.2
±1
±100
±1
±100
mA
µA
µA
mA
mA
µA
V
CC
=Max., V
OUT
=2.7V
V
CC
=Max., V
OUT
=0.5V
V
CC
=Max., V
OUT
=GND
V
CC
=Max., V
OUT
=2.5V
V
CC
=0V, V
OUT
≤4.5V
[11]
Output Drive Characteristics for CY74FCT16952T
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
V
CC
=Min., I
OH
= –3 mA
V
CC
=Min., I
OH
= –15 mA
V
CC
=Min., I
OH
= –32 mA
V
OL
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
Min.
2.5
2.4
2.0
Typ.
[7]
3.5
3.5
3.0
0.2
0.55
Max.
Unit
V
V
V
V
Output Drive Characteristics for CY74FCT162952T, CY74FCT162H952T
Parameter
I
ODL
I
ODH
V
OH
V
OL
Description
Output LOW Current
[10]
Output HIGH Current
[10]
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=5V, V
IN
=V
IH
or V
IL
, V
OUT
=1.5V
V
CC
=Min., I
OH
= –24 mA
V
CC
=Min., I
OL
=24 mA
Min.
60
–60
2.4
Typ.
[7]
115
–115
3.3
0.3
0.55
Max.
150
–150
Unit
mA
mA
V
V
Capacitance
[8]
(T
A
= +25°C, f = 1.0 MHz)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
Test Conditions
Typ.
[7]
4.5
5.5
Max.
6.0
8.0
Unit
pF
pF
Note:
7. Typical values are at V
CC
= 5.0V, T
A
= +25°C ambient.
8. This parameter is guaranteed but not tested.
9. Pins with bus hold are described in the Pin Description.
10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a
high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests,
I
OS
tests should be performed last.
11. Tested at +25°C.
3
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Quiescent Power Supply Current V
CC
=Max.
Quiescent Power Supply Current V
CC
=Max.
(TTL inputs HIGH)
Dynamic Power Supply
Current
[14]
Total Power Supply Current
[15]
Test Conditions
[12]
V
IN
<0.2V
V
IN
>V
CC
–0.2V
V
IN
=3.4V
[13]
Typ.
[7]
5
0.5
75
Max.
500
1.5
120
Unit
µA
mA
µA/MHz
V
CC
=Max., One Input Toggling, V
IN
=V
CC
or
50% Duty Cycle, Outputs Open, V
IN
=GND
OEAB or OEBA=GND
V
CC
=Max., F
1
=5 MHz,
F
0
= 10 MHz (CLKAB)
OEAB = CEAB = GND
OEBA = V
CC
50% Duty Cycle,
Outputs Open, One Bit Toggling
V
CC
=Max., f
0
=10 MHz (CLKAB)
f
1
=2.5 MHz,
OEAB = CEAB = GND
OEBA = V
CC
50% Duty Cycle,
Outputs Open,
Sixteen Bit Toggling
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
V
IN
=V
CC
or
V
IN
=GND
V
IN
=3.4V or
V
IN
=GND
I
C
0.8
1.3
3.8
8.3
1.7
3.2
6.5
[16]
20.0
[16]
mA
Notes:
12. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
13. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
15. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f
0
f
1
= Input signal frequency
N
1
= Number of inputs changing at f
1
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
4
CY74FCT16952T
CY74FCT162952T
CY74FCT162H952T
Switching Characteristics
Over the Operating Range
[17]
CY74FCT16952AT
CY74FCT162952AT
CY74FCT162H952AT
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK(O)
Description
Propagation Delay
CLKAB, CLKBA to B, A
Output Enable Time
OEBA, OEAB to A, B
Output Disable Time
OEBA, OEAB to A, B
Set-Up Time, HIGH or LOW
A, B to CLKAB, CLKBA
Hold Time, HIGH or LOW
A, B to CLKAB, CLKBA
Set-Up Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
Hold Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
Pulse Width HIGH or LOW
CLKAB or CLKBA
[19]
Output Skew
[20]
Min.
2.0
1.5
1.5
2.5
2.0
3.0
2.0
3.0
—
Max.
10.0
10.5
10.0
—
—
—
—
—
0.5
CY74FCT16952BT
CY74FCT162952BT
CY74FCT162H952BT
Min.
2.0
1.5
1.5
2.5
1.5
3.0
2.0
3.0
—
Max.
7.5
8.0
7.5
—
—
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[18]
1, 5
1, 7, 8
1, 7, 8
4
4
4
4
5
—
CY74FCT16952CT
CY74FCT162952CT
CY74FCT162H952CT
Parameter
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK(O)
Description
Propagation Delay
CLKAB, CLKBA to B, A
Output Enable Time
OEBA, OEAB to A, B
Output Disable Time
OEBA, OEAB to A, B
Set-Up Time, HIGH or LOW
A, B to CLKAB, CLKBA
Hold Time, HIGH or LOW
A, B to CLKAB, CLKBA
Set-Up Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
Hold Time, HIGH or LOW
CEAB, CEBA to CLKAB, CLKBA
Pulse Width HIGH or LOW
CLKAB or CLKBA
[19]
Output Skew
[20]
Min.
2.0
1.5
1.5
2.5
1.5
3.0
2.0
3.0
—
Max.
6.3
7.0
6.5
—
—
—
—
—
0.5
CY74FCT16952ET
CY74FCT162952ET
CY74FCT162H952ET
Min.
1.5
1.5
1.5
1.5
0
2.0
0
3.0
—
Max.
3.7
4.4
3.6
—
—
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[18]
1, 5
1, 7, 8
1, 7, 8
4
4
4
4
5
—
Notes:
17. Minimum limits are guaranteed but not tested on Propagation Delays.
18. See “Parameter Measurement Information” in the General Information section.
19. This parameter is guaranteed but not tested.
20. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.